公开(公告)号：US20090061588A1

公开(公告)日：2009-03-05

申请号：US11969924

申请日：2008-01-07

Applicant: Chang-Ho Yeh ,  Hong-Wen Lee

Inventor： Chang-Ho Yeh ,  Hong-Wen Lee

IPC: H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876

Abstract: A method for fabricating a dynamic random access memory is provided. A substrate having two trench capacitors therein is provided, an isolation structure protruding from a surface of the substrate is formed on each trench capacitor, a spacer is formed on the substrate at two sides of each of the isolation structures, and a block layer is formed between each spacer and each isolation structure and between each spacer and the substrate. A trench is formed in the substrate between the trench capacitors, and partial of the trench is located under partial of the spacers and partial of the block layer. The spacers, the block layer, and partial of the isolation structures above the trench are removed. A gate structure protruding from the surface of the substrate is formed in the trench. A doped region is formed in the substrate at each of two sides of the gate structure.

Abstract translation: 提供了一种用于制造动态随机存取存储器的方法。 提供一种其中具有两个沟槽电容器的衬底，在每个沟槽电容器上形成从衬底表面突出的隔离结构，在每个隔离结构的两侧在衬底上形成间隔物，形成阻挡层 在每个间隔物和每个隔离结构之间以及每个间隔物和基底之间。 在沟槽电容器之间的衬底中形成沟槽，并且沟槽的部分位于衬垫的部分部分和阻挡层的部分之下。 去除间隔物，阻挡层和沟槽上方的隔离结构的部分。 在沟槽中形成从衬底表面突出的栅极结构。 在栅极结构的两侧的每一侧的基板中形成掺杂区域。

公开(公告)号：US07569451B2

公开(公告)日：2009-08-04

申请号：US11969913

申请日：2008-01-06

Applicant: Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

Inventor： Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

IPC: H01L21/8242

CPC classification number: H01L21/763 ,  H01L21/76232 ,  H01L27/1087

Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

Abstract translation: 制造隔离浅沟槽的方法包括：提供具有至少深沟槽的衬底，在深沟槽的上部形成覆盖层，在覆盖层的一部分上形成外壳层，限定延伸穿过该沟槽的沟槽 盖层和导电层，并在浅沟槽中形成隔离层。

公开(公告)号：US20080146031A1

公开(公告)日：2008-06-19

申请号：US12000538

申请日：2007-12-13

Applicant: Hung Jen Liu ,  Wei Hsien Hsieh ,  Chang-Ho Yeh

Inventor： Hung Jen Liu ,  Wei Hsien Hsieh ,  Chang-Ho Yeh

IPC: H01L21/461

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method for semiconductor structure formation includes: providing a substrate; forming a first lower mask layer on the substrate; forming a first patterned mask on the first lower mask layer; forming a second lower mask layer on the first lower mask layer and overlaying the first patterned mask; forming a second patterned mask on the second lower mask layer without the second patterned mask overlapping the first patterned mask; etching and undercutting the first lower mask layer and the second lower mask layer to form the third patterned mask with the first patterned mask and the second patterned mask; etching the substrate by using the third patterned mask to form a plurality of islands; and removing the third patterned mask.

Abstract translation: 一种用于半导体结构形成的方法包括：提供衬底; 在所述基板上形成第一下掩模层; 在所述第一下掩模层上形成第一图案化掩模; 在所述第一下掩模层上形成第二下掩模层并覆盖所述第一图案掩模; 在所述第二下掩模层上形成第二图案化掩模，而所述第二图案掩模与所述第一图案掩模重叠; 蚀刻和底切第一下掩模层和第二下掩模层，以形成具有第一图案化掩模和第二图案掩模的第三图案化掩模; 通过使用第三图案化掩模蚀刻衬底以形成多个岛; 并去除第三图案掩模。

公开(公告)号：US07303960B1

公开(公告)日：2007-12-04

申请号：US11695052

申请日：2007-04-01

Applicant: Chang-Ho Yeh ,  Chang-Ming Wu ,  Jhong-Ciang Min

Inventor： Chang-Ho Yeh ,  Chang-Ming Wu ,  Jhong-Ciang Min

IPC: H01L21/8247

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method for fabricating a flash memory device including the steps of: providing a substrate having thereon a gate with therein a control gate; lining the substrate and the gate with a liner; forming a silicon layer on the liner; forming a sacrificing layer on the silicon layer; etching the sacrificing layer to expose a portion of the silicon layer; removing the exposed silicon layer to expose a portion of the liner; removing the sacrificing layer; forming a spacer layer on the substrate covering the remaining silicon layer and the exposed liner; etching the spacer layer to form a spacer on sidewall of the gate; and removing the silicon layer that is not covered by the spacer thereby forming floating gate on sidewall of the gate.

Abstract translation: 一种用于制造闪速存储器件的方法，包括以下步骤：在其上提供其上具有栅极的基板;控制栅极; 用衬垫衬底和门; 在衬垫上形成硅层; 在所述硅层上形成牺牲层; 蚀刻牺牲层以暴露一部分硅层; 去除暴露的硅层以露出衬垫的一部分; 去除牺牲层; 在覆盖剩余硅层和暴露的衬垫的衬底上形成间隔层; 蚀刻间隔层以在栅极的侧壁上形成间隔物; 并且去除未被间隔物覆盖的硅层，从而在栅极的侧壁上形成浮栅。

公开(公告)号：US20080286935A1

公开(公告)日：2008-11-20

申请号：US11969913

申请日：2008-01-06

Applicant: Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

Inventor： Jen-Jui Huang ,  Hsiu-Chun Lee ,  Chang-Ho Yeh

IPC: H01L21/76

CPC classification number: H01L21/763 ,  H01L21/76232 ,  H01L27/1087

Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

Abstract translation: 制造隔离浅沟槽的方法包括：提供具有至少深沟槽的衬底，在深沟槽的上部形成覆盖层，在覆盖层的一部分上形成外壳层，限定延伸穿过该沟槽的沟槽 盖层和导电层，并在浅沟槽中形成隔离层。