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公开(公告)号：US07793025B2
公开(公告)日：2010-09-07
申请号：US12057989
申请日：2008-03-28
申请人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
发明人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
CPC分类号： G06F13/26
摘要： A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.
摘要翻译： 提供了一种灵活的中断控制器电路和方法，其使用中断电路（300），该中断电路（300）基于在模式控制选择器（326）中识别的系统的当前上下文复用（324）多个中断优先级寄存器（321,322） ）。 通过使用模式控制选择器（326）选择性地将不同的优先级分配耦合到优先级编码模块（330），可以以降低的等待时间来实现分配给每个中断请求的优先级的上下文敏感切换。 上下文切换可以基于OS上下文ID，电源管理模式，安全模式和其他优先级别不同的系统定义模式。 所选择的优先级信息用于提供将在数据处理系统中发生中断的中断请求信号（332）。
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公开(公告)号：US07747889B2
公开(公告)日：2010-06-29
申请号：US11461048
申请日：2006-07-31
CPC分类号： H04L7/00 , H04L7/0008
摘要： A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.
摘要翻译： 数据处理系统可以包括具有输出的发起者设备，其输出单独对应于沿着信令路径的第一延迟的时钟输入引用。 示例性数据处理系统还可以包括具有输入的目标设备，其输入单独对应于沿着信令路径的第二延迟的时钟输入和在信令路径内的起始设备和目标设备之间互连的系统总线 。 示例性数据处理系统还可以包括耦合到信令路径内的系统总线的动态定时桥，其中响应于表示至少一个系统特性的控制信号，动态定时桥执行从由（i ）在信令路径内插入循环延迟，并且（ii）不在信令路径内插入循环等待时间。
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公开(公告)号：US07099973B2
公开(公告)日：2006-08-29
申请号：US10402165
申请日：2003-03-26
CPC分类号： G06F13/364
摘要： A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and second storage locations store bus master parking information for a system bus (141). The arbiter (150) receives a parking context indicator (131) that is used to select one of the first and second storage locations (151, 152) to provide bus master parking information to the arbiter (150).
摘要翻译： 公开了具有耦合到仲裁器（150）的多个总线主机（111-113）的系统（100）。 仲裁器（150）耦合到第一存储位置（151）和第二存储位置（152），其中第一和第二存储位置存储用于系统总线（141）的总线主站停车信息。 仲裁器（150）接收用于选择第一和第二存储位置（151,152）之一以便向仲裁器（150）提供总线主机停车信息的停车上下文指示器（131）。
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公开(公告)号：US20090248935A1
公开(公告)日：2009-10-01
申请号：US12057989
申请日：2008-03-28
申请人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
发明人： Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
IPC分类号： G06F13/24
CPC分类号： G06F13/26
摘要： A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.
摘要翻译： 提供了一种灵活的中断控制器电路和方法，其使用中断电路（300），该中断电路（300）基于在模式控制选择器（326）中识别的系统的当前上下文复用（324）多个中断优先级寄存器（321,322） ）。 通过使用模式控制选择器（326）选择性地将不同的优先级分配耦合到优先级编码模块（330），可以以降低的等待时间来实现分配给每个中断请求的优先级的上下文敏感切换。 上下文切换可以基于OS上下文ID，电源管理模式，安全模式和其他优先级别不同的系统定义模式。 所选择的优先级信息用于提供将在数据处理系统中发生中断的中断请求信号（332）。
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公开(公告)号：US07353311B2
公开(公告)日：2008-04-01
申请号：US11142148
申请日：2005-06-01
CPC分类号： G06F13/4022
摘要： A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.
摘要翻译： 公开了一种方法，其中基于与每个交易相关联的交易标识符来确定能够在公共时间处理的交易中的优先级。 事务标识符可以直接指示事务之间的优先级，或用于索引指示优先级值的存储位置。 可以基于预定义的标准，将请求设备或其他优先级确定模块的交易标识符选择为与交易相关联。
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公开(公告)号：US07124281B1
公开(公告)日：2006-10-17
申请号：US09667122
申请日：2000-09-21
IPC分类号： G06F9/00
CPC分类号： G06F13/28
摘要： Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus for providing a current address and a previous address to memory, a data bus, an execution unit, and a decode control unit. The processing system further includes a fetch unit, coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.
摘要翻译： 本发明的实施例涉及具有顺序地址指示符信号的处理器，也称为序列信号，用于指示何时访问的地址是顺序的。 一个实施例涉及一种用于访问具有用于向存储器提供当前地址和前一地址的地址总线的存储器的处理系统，数据总线，执行单元和解码控制单元。 该处理系统还包括一个提取单元，耦合到执行单元，解码控制单元，地址总线和数据总线，用于产生一个第一序列信号，当被否定时指示当前地址可能不与先前的 地址，当被否定时指示当前地址不与先前地址顺序的第二序列信号，以及当被否定时的第三序列信号指示当前地址（如果是指令地址）不是与先前地址相连 那是一个指示地址。
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公开(公告)号：US07340542B2
公开(公告)日：2008-03-04
申请号：US10955558
申请日：2004-09-30
申请人： William C. Moyer , Brett W. Murdock
发明人： William C. Moyer , Brett W. Murdock
IPC分类号： G06F3/00
CPC分类号： G06F13/368
摘要： A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
摘要翻译： 总线主控器可以基于当前挂起的访问的一个或多个特征来选择性地撤回当前未决的访问。 以这种方式，总线主控可以更好地控制其访问请求。 一个或多个特征可以包括例如访问的类型（例如读/写，指令/数据，突发/非突发等），访问的顺序或顺序，被访问的地址（例如哪个地址范围是 访问或正在访问哪个设备），总线主机请求撤回（在例如多主机系统中）或其任何组合。 总线仲裁器还可以基于当前待决的访问请求或后续访问请求的一个或多个特征来选择性地撤回当前待决的访问请求，以有利于后续的访问请求。 这些特征可以包括上面列出的任何一个，请求主人的优先级（例如请求主人之间的优先级增量），请求主人的其他属性或其任何组合。
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公开(公告)号：US20080028253A1
公开(公告)日：2008-01-31
申请号：US11461048
申请日：2006-07-31
IPC分类号： G06F1/04
CPC分类号： H04L7/00 , H04L7/0008
摘要： A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.
摘要翻译： 数据处理系统可以包括具有输出的发起者设备，其输出单独对应于沿着信令路径的第一延迟的时钟输入引用。 示例性数据处理系统还可以包括具有输入的目标设备，其输入单独对应于沿着信令路径的第二延迟的时钟输入和在信令路径内的起始设备和目标设备之间互连的系统总线 。 示例性数据处理系统还可以包括耦合到信令路径内的系统总线的动态定时桥，其中响应于表示至少一个系统特性的控制信号，动态定时桥执行从由（i ）在信令路径内插入循环延迟，并且（ii）不在信令路径内插入循环等待时间。
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公开(公告)号：US07185121B2
公开(公告)日：2007-02-27
申请号：US11203935
申请日：2005-08-15
IPC分类号： G06F13/28
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.
摘要翻译： 交叉开关（12）仲裁用于从多个总线主机（14,16,18,20和22）到具有重叠地址范围的多个寻址从端口（3和4）的访问。 在一种形式中，地址范围是相同的地址范围。 当所有寻址端口都忙时，交叉开关（12）使用共享从端口控制电路（48），配置寄存器（46）和从端口仲裁器逻辑（34,36,38,40,42和44）仲裁访问 。 确定新的访问请求是否比现有访问的优先级更高或更低。 基于对包括所请求的数据跳动的数量以及等待状态信息的各种因素的预测，首先将确定某个多个访问中的哪一个将首先完成，从而确定何时引导新的访问请求。 在一种模式中，动态地确定等待状态信息。
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公开(公告)号：US07130943B2
公开(公告)日：2006-10-31
申请号：US10954809
申请日：2004-09-30
CPC分类号： G06F13/362
摘要： A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
摘要翻译： 总线主控器可以基于当前挂起的访问的一个或多个特征来选择性地撤回当前未决的访问。 以这种方式，总线主控可以更好地控制其访问请求。 一个或多个特征可以包括例如访问的类型（例如读/写，指令/数据，突发/非突发等），访问的顺序或顺序，被访问的地址（例如哪个地址范围是 访问或正在访问哪个设备），总线主机请求撤回（在例如多主机系统中）或其任何组合。 总线仲裁器还可以基于当前待决的访问请求或后续访问请求的一个或多个特征来选择性地撤回当前待决的访问请求，以有利于后续的访问请求。 这些特征可以包括上面列出的任何一个，请求主机的优先级（例如请求主机之间的优先级增量），请求主机的其他属性或其任何组合。
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