发明授权
US07340542B2 Data processing system with bus access retraction 有权
数据处理系统与总线访问回退

  • 专利标题: Data processing system with bus access retraction
  • 专利标题(中): 数据处理系统与总线访问回退
  • 申请号: US10955558
    申请日: 2004-09-30
  • 公开(公告)号: US07340542B2
    公开(公告)日: 2008-03-04
  • 发明人: William C. MoyerBrett W. Murdock
  • 申请人: William C. MoyerBrett W. Murdock
  • 代理商 Joanna G. Chiu; Robert L. King; Ranjeev Singh
  • 主分类号: G06F3/00
  • IPC分类号: G06F3/00
Data processing system with bus access retraction
摘要:
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
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