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    Bandwidth division for packet processing
    2.
    发明授权
    Bandwidth division for packet processing 失效
    分组处理带宽划分

    公开(公告)号：US08081654B2

    公开(公告)日：2011-12-20

    申请号：US12723303

    申请日：2010-03-12

    申请人： Stefan Dyckerhoff ,  Pankaj Patel ,  Pradeep Sindhu ,  Ashok Krishnamurthi ,  Hann-Hwan Ju ,  Ramalingam Krishnamurthi Anand

    发明人： Stefan Dyckerhoff ,  Pankaj Patel ,  Pradeep Sindhu ,  Ashok Krishnamurthi ,  Hann-Hwan Ju ,  Ramalingam Krishnamurthi Anand

    IPC分类号： H04J3/16

    CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L47/125 ,  H04L49/103 ,  H04L49/45 ,  H04L49/552

    摘要： A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth.

    摘要翻译： 一种用于在多个分组处理器之间分配带宽的带宽分配器和方法。 带宽分配器包括多个计数器，用于测量从带宽分配器传输到相应分组处理器的数据分组的带宽; 以及用于分析所述多个计数器并基于所述计数器的内容将数据分组传送到所选分组处理器的控制器。 该方法监视分组处理器消耗的带宽; 基于分组处理器消耗的带宽来确定哪个分组处理器消耗的带宽最小; 并将下一个数据分组分配给消耗最少带宽的分组处理器。

    Bandwidth division for packet processing
    3.
    发明授权
    Bandwidth division for packet processing 有权
    分组处理带宽划分

    公开(公告)号：US07706357B1

    公开(公告)日：2010-04-27

    申请号：US11470040

    申请日：2006-09-05

    申请人： Stefan Dyckerhoff ,  Pankaj Patel ,  Pradeep Sindhu ,  Ashok Krishnamurthi ,  Hann-Hwan Ju ,  Ramalingam K. Anand

    发明人： Stefan Dyckerhoff ,  Pankaj Patel ,  Pradeep Sindhu ,  Ashok Krishnamurthi ,  Hann-Hwan Ju ,  Ramalingam K. Anand

    IPC分类号： H04L12/66

    CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L47/125 ,  H04L49/103 ,  H04L49/45 ,  H04L49/552

    摘要： A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth.

    摘要翻译： 一种用于在多个分组处理器之间分配带宽的带宽分配器和方法。 带宽分配器包括多个计数器，用于测量从带宽分配器传输到相应分组处理器的数据分组的带宽; 以及用于分析所述多个计数器并基于所述计数器的内容将数据分组传送到所选分组处理器的控制器。 该方法监视分组处理器消耗的带宽; 基于分组处理器消耗的带宽来确定哪个分组处理器消耗的带宽最小; 并将下一个数据分组分配给消耗最少带宽的分组处理器。

    Diagnostic access to processors in a complex electrical system
    4.
    发明授权
    Diagnostic access to processors in a complex electrical system 有权
    在复杂电气系统中诊断访问处理器

    公开(公告)号：US06826713B1

    公开(公告)日：2004-11-30

    申请号：US09751937

    申请日：2001-01-02

    申请人： Michael Beesley ,  Ross Heitkamp ,  Ashok Krishnamurthi ,  Kenneth Richard Powell

    发明人： Michael Beesley ,  Ross Heitkamp ,  Ashok Krishnamurthi ,  Kenneth Richard Powell

    IPC分类号： G06F1100

    CPC分类号： G06F11/3495 ,  G06F11/3636

    摘要： A debugging and diagnostic system allows a developer to receive low-level diagnostic information from multiple processors in a complex electrical system. A bus connects a master processor to the processors to be debugged via corresponding receiver/driver circuits. The receiver/driver circuits receive serial information from the processors and transmit it to the bus. The master processor controls the receiver/driver circuits through a control logic circuit.

    摘要翻译： 调试和诊断系统允许开发人员从复杂的电气系统中的多个处理器接收低级诊断信息。 总线通过相应的接收器/驱动器电路将主处理器连接到要调试的处理器。 接收器/驱动器电路从处理器接收串行信息并将其发送到总线。 主处理器通过控制逻辑电路控制接收器/驱动器电路。

    Apparatus and method for directing airflow in three dimensions to cool system components
    7.
    发明授权
    Apparatus and method for directing airflow in three dimensions to cool system components 有权
    用于引导三维空气流冷却系统部件的装置和方法

    公开(公告)号：US06459579B1

    公开(公告)日：2002-10-01

    申请号：US09752824

    申请日：2001-01-03

    申请人： Daniel Fairchild Farmer ,  Ashok Krishnamurthi ,  Richard Singer ,  Ali Mira

    发明人： Daniel Fairchild Farmer ,  Ashok Krishnamurthi ,  Richard Singer ,  Ali Mira

    IPC分类号： H05K720

    CPC分类号： H05K7/20736

    摘要： The invention provides forced-air cooling to components mounted on circuit boards oriented in a side-to-side direction in a system. Airflow may enter and exit the system through the front and back (or vice-versa), rather than the sides of the system. In one embodiment, airflow entering the front of the system is re-directed in an upward direction, then split to form airflow branches traversing in a side-to-side direction. The airflow branches traverse across the surfaces of circuit boards, then are directed in an upward direction and out the back (or front) of the system. The airflow branches preferably move substantially the same volume of air per unit of time.

    摘要翻译： 本发明为系统中沿着侧向方向定向的电路板上安装的部件提供强制空气冷却。 气流可以通过前后（或反之亦然）进入和离开系统，而不是系统的两侧。 在一个实施例中，进入系统前部的气流在向上方向上被重新定向，然后被分开以形成沿着侧向方向横穿的气流分支。 气流分支穿过电路板的表面，然后沿向上的方向被引导到系统的后部（或前部）。 气流分支优选地每单位时间基本上移动相同体积的空气。

    Wireless host I/O using virtualized I/O controllers
    9.
    发明授权
    Wireless host I/O using virtualized I/O controllers 有权
    使用虚拟化I / O控制器的无线主机I / O

    公开(公告)号：US09331963B2

    公开(公告)日：2016-05-03

    申请号：US12890498

    申请日：2010-09-24

    申请人： Ashok Krishnamurthi ,  Ariel Cohen

    发明人： Ashok Krishnamurthi ,  Ariel Cohen

    IPC分类号： G06F3/00 ,  H04L12/861 ,  G06F3/06 ,  G06F9/455 ,  H04L12/801 ,  H04L29/08

    CPC分类号： H04L49/90 ,  G06F3/061 ,  G06F3/0661 ,  G06F3/0664 ,  G06F3/067 ,  G06F9/45558 ,  H04L47/10 ,  H04L67/1097

    摘要： Mechanisms provide hosts such as servers and mobile devices with access to virtualized I/O resources including virtual Host Bus Adapters (vHBAs) and virtual Network Interface Cards (vNICs) over a wireless I/O interconnect. Host applications access virtualized I/O resources using virtual device drivers that communicate with virtualized I/O resources on an I/O director using a reliable communication protocol running over a wireless network. I/O data is throttled if necessary based on wireless network considerations.

    摘要翻译： 机制为诸如服务器和移动设备之类的主机提供通过无线I / O互连访问虚拟I / O资源，包括虚拟主机总线适配器（vHBA）和虚拟网络接口卡（vNIC）。 使用通过无线网络运行的可靠通信协议，使用虚拟设备驱动程序访问虚拟化I / O资源的主机应用程序可以访问I / O控制器上的虚拟化I / O资源。 如果需要，则基于无线网络考虑，I / O数据被限制。

    High-speed line interface for networking devices
    10.
    发明授权
    High-speed line interface for networking devices 有权
    网络设备的高速线路接口

    公开(公告)号：US07164698B1

    公开(公告)日：2007-01-16

    申请号：US09752827

    申请日：2001-01-03

    申请人： Ashok Krishnamurthi ,  Jeffrey Scott Dredge ,  Ramesh Padmanabhan ,  Ramalingam K. Anand

    发明人： Ashok Krishnamurthi ,  Jeffrey Scott Dredge ,  Ramesh Padmanabhan ,  Ramalingam K. Anand

    IPC分类号： H04J3/02

    CPC分类号： H04J3/1617 ,  H04J2203/0008 ,  H04J2203/0025

    摘要： Systems and methods, consistent with the present invention, provide a high-speed line interface for networking devices. Such an interface may be used in networking devices, such as routers and switches, for receiving data from, and transmitting data to, high-speed links, such as those lines carrying data at rates of 2.5 Gbit/sec, 10 Gbit/sec, and 40 Gbit/sec and more. In a preferred embodiment, the interface deserializes data from an incoming data stream onto a multi-line bus so that the data may be processed at a lower clock speed. Packets are extracted from the data on the multi-line bus and distributed among a plurality of switching/forwarding modules for processing.

    摘要翻译： 与本发明一致的系统和方法为网络设备提供高速线路接口。 这样的接口可以用于诸如路由器和交换机之类的网络设备中，用于从高速链路接收数据，并向高速链路发送数据，例如以2.5Gbit / sec，10Gbit / sec的速率传送数据的那些线路， 和40 Gbit /秒以上。 在优选实施例中，接口将来自输入数据流的数据反序列化到多线总线上，使得可以以更低的时钟速度处理数据。 从多线总线上的数据提取分组，并分配在多个交换/转发模块之间进行处理。