Interfacing with streams of differing speeds
    1.
    发明授权
    Interfacing with streams of differing speeds 有权
    接触不同速度的流

    公开(公告)号:US08131854B2

    公开(公告)日:2012-03-06

    申请号:US12698794

    申请日:2010-02-02

    IPC分类号: G06F15/173

    摘要: A system processes packet data received in a number of incoming streams of variable speeds. The system includes an input interface, input logic, and one or more packet processors. The input interface receives the packet data and outputs the data using a first arbitration element. The input logic includes flow control logic, a memory, and a dispatch unit. The flow control logic initiates flow control on the data output by the input interface. The memory stores the data from the input interface. The dispatch unit reads the data from the memory using a second arbitration element. The packet processor(s) process the data from the dispatch unit.

    摘要翻译: 系统处理以多个可变速度的输入流接收的分组数据。 该系统包括输入接口,输入逻辑和一个或多个分组处理器。 输入接口接收分组数据并使用第一仲裁元素输出数据。 输入逻辑包括流控制逻辑,存储器和调度单元。 流量控制逻辑启动由输入接口输出的数据的流量控制。 存储器存储来自输入接口的数据。 调度单元使用第二仲裁元素从存储器读取数据。 分组处理器处理来自分派单元的数据。

    SYSTEMS AND METHODS FOR PRESERVING THE ORDER OF DATA
    3.
    发明申请
    SYSTEMS AND METHODS FOR PRESERVING THE ORDER OF DATA 有权
    保存数据订单的系统和方法

    公开(公告)号:US20070220189A1

    公开(公告)日:2007-09-20

    申请号:US11752620

    申请日:2007-05-23

    IPC分类号: G06F13/00

    摘要: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

    摘要翻译: 一种装置包括输入处理单元和输出处理单元。 输入处理单元将第一数据分配到一组处理引擎中的一个,将一个处理引擎的标识记录在第一存储器中的位置中,在第二存储器中保留一个或多个对应位置,使得第一数据被处理 并且将经处理的第一数据存储在第二存储器中的一个位置中。 输出处理单元接收第二数据,将对应于输出存储器中的位置的入口地址分配给第二数据,将第二数据和入口地址传送给一组第二处理引擎,使得第二数据被处理 并且将处理的第二数据存储到输出存储器中的位置。

    Bandwidth division for packet processing
    4.
    发明授权
    Bandwidth division for packet processing 失效
    分组处理带宽划分

    公开(公告)号:US08081654B2

    公开(公告)日:2011-12-20

    申请号:US12723303

    申请日:2010-03-12

    IPC分类号: H04J3/16

    摘要: A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth.

    摘要翻译: 一种用于在多个分组处理器之间分配带宽的带宽分配器和方法。 带宽分配器包括多个计数器,用于测量从带宽分配器传输到相应分组处理器的数据分组的带宽; 以及用于分析所述多个计数器并基于所述计数器的内容将数据分组传送到所选分组处理器的控制器。 该方法监视分组处理器消耗的带宽; 基于分组处理器消耗的带宽来确定哪个分组处理器消耗的带宽最小; 并将下一个数据分组分配给消耗最少带宽的分组处理器。

    Bandwidth division for packet processing
    5.
    发明授权
    Bandwidth division for packet processing 有权
    分组处理带宽划分

    公开(公告)号:US07706357B1

    公开(公告)日:2010-04-27

    申请号:US11470040

    申请日:2006-09-05

    IPC分类号: H04L12/66

    摘要: A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth.

    摘要翻译: 一种用于在多个分组处理器之间分配带宽的带宽分配器和方法。 带宽分配器包括多个计数器,用于测量从带宽分配器传输到相应分组处理器的数据分组的带宽; 以及用于分析所述多个计数器并基于所述计数器的内容将数据分组传送到所选分组处理器的控制器。 该方法监视分组处理器消耗的带宽; 基于分组处理器消耗的带宽来确定哪个分组处理器消耗的带宽最小; 并将下一个数据分组分配给消耗最少带宽的分组处理器。

    Interfacing with streams of differing speeds
    7.
    发明授权
    Interfacing with streams of differing speeds 有权
    接触不同速度的流

    公开(公告)号:US07698454B1

    公开(公告)日:2010-04-13

    申请号:US09991109

    申请日:2001-11-26

    IPC分类号: G06F15/173

    摘要: A system processes packet data received in a number of incoming streams of variable speeds. The system includes an input interface, input logic, and one or more packet processors. The input interface receives the packet data and outputs the data using a first arbitration element. The input logic includes flow control logic, a memory, and a dispatch unit. The flow control logic initiates flow control on the data output by the input interface. The memory stores the data from the input interface. The dispatch unit reads the data from the memory using a second arbitration element. The packet processor(s) process the data from the dispatch unit.

    摘要翻译: 系统处理以多个可变速度的输入流接收的分组数据。 该系统包括输入接口,输入逻辑和一个或多个分组处理器。 输入接口接收分组数据并使用第一仲裁元素输出数据。 输入逻辑包括流控制逻辑,存储器和调度单元。 流量控制逻辑启动由输入接口输出的数据的流量控制。 存储器存储来自输入接口的数据。 调度单元使用第二仲裁元素从存储器读取数据。 分组处理器处理来自分派单元的数据。