公开(公告)号：US07446968B2

公开(公告)日：2008-11-04

申请号：US11188391

申请日：2005-07-25

申请人： Davide Giovenzana ,  Angelo Dati ,  Augusto Andrea Rossi

发明人： Davide Giovenzana ,  Angelo Dati ,  Augusto Andrea Rossi

IPC分类号： G11B5/09

CPC分类号： G11B20/10009 ,  G11B20/10055 ,  G11B20/10222 ,  H04L7/0029 ,  H04L7/10

摘要： The method and architecture improve the robustness of a synchronization system through a minimum latency loop, for Hard Disk Drives (HDD), for example, wherein synchronous detection processing is performed for timing recovering of a correct sampling phase and frequency and by a first acquisition step of a known preamble signal pattern, for generating a timing periodic signal, followed by a second tracking step, for recovering phase, frequency and gain sampling errors of the synchronization signal including a header followed by an unknown data content. Advantageously, a feedback loop including a numeric preamble generator (NPG) is provided for obtaining a reduced latency in the acquisition phase. The NPG stores preamble values for different phase offset.

摘要翻译： 该方法和体系结构通过最小等待时间环路来改善对于硬盘驱动器（HDD）的同步系统的鲁棒性，例如，其中执行用于定时恢复正确采样相位和频率的同步检测处理，以及通过第一获取步骤 用于产生定时周期信号，随后是第二跟踪步骤，用于恢复同步信号的相位，频率和增益采样误差，所述同步信号包括后跟未知数据内容的报头。 有利地，提供包括数字前导码生成器（NPG）的反馈回路，用于在获取阶段获得减小的等待时间。 NPG存储不同相位偏移的前导码。

公开(公告)号：US07430704B2

公开(公告)日：2008-09-30

申请号：US11025769

申请日：2004-12-20

申请人： Angelo Dati ,  Pierandrea Savo ,  Ezio Iacazio ,  Kelly Fitzpatrick ,  John J. McEwen, legal representative ,  Bahjat Zafer

发明人： Peter McEwen

IPC分类号： H03M13/03

CPC分类号： G11B20/10009

摘要： A method for detecting signals affected by intersymbol interference provides for a path memory in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length λ. The first stage outputs a first state SAkk-λ on the survivor path for the best state Ak, and a second state SBkk-λ on the survivor path for another state Bk. The second stage is configured as a two-state shift register exchange having a respective memory length Λ, including respective first and second registers. In the respective first and second registers the survivor paths are stored leading to a respective first σ0k and second σ1k state, whereby the respective first register contains the backend of the best survivor path, while the respective second register contains the backend of an alternative survivor path.

摘要翻译： 用于检测由符号间干扰影响的信号的方法提供以包含第一和第二阶段的遗体路径形式的网格形式的路径存储器。 第一级包括具有给定数量的状态和给定长度λ的移位寄存器交换。 第一级在幸存路径上输出最佳状态A N的第一状态S K 和第二状态S < 在另一状态B 的幸存路径上的SUP> Bk k-lambda 。 第二级被配置为具有各自的存储器长度Lambda的双态移位寄存器交换机，包括相应的第一和第二寄存器。 在相应的第一和第二寄存器中存储了幸存路径，导致相应的第一西格尔＆lt; 0＆gt;和第二西格尔＆lt; 1＆gt; / SUB>状态，由此相应的第一寄存器包含最佳幸存路径的后端，而相应的第二寄存器包含备用幸存路径的后端。

公开(公告)号：US07203884B2

公开(公告)日：2007-04-10

申请号：US10409634

申请日：2003-04-07

申请人： Angelo Dati ,  Augusto Rossi ,  Davide Giovenzana

发明人： Angelo Dati ,  Augusto Rossi ,  Davide Giovenzana

IPC分类号： H03M13/00

CPC分类号： H03M13/41 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/1426 ,  G11B20/1803 ,  G11B2005/0029 ,  H03M5/145 ,  H03M7/46 ,  H03M13/31 ,  H03M13/6312 ,  H03M13/6343

摘要： In the MSN encoded form, the symbols of each block of the present invention define a running digital sum (RDS) value, defined as RDS([a0a1 . . . aN−1])=−Σi(−1)ai where the symbols ai belong to the set {0, 1} and the sum extends for values of i from 0 to N−1. An encoder is configured to satisfy at least one of the following characteristics: a) blocks of symbols with a given length (L) are used for encoding, wherein RDS=RDS0+4.K, where K is an integer, RDS is the said running digital sum, RDS0 is defined as zero for even values of the said length (L), and one for odd values of said length (L), and b) blocks of symbols with a given length (L) are used for MSN coding and encoding is effected by selecting encoded blocks such that the set of running digital sum (RDS) values is the set with the minimum number of elements that satisfy the required rate value, defined as the ratio between the length of the input blocks and the length of the output blocks. A decoder with a simplified trellis structure is used for decoding (as in decoding a digital signal read from media on which the signal in question has been recorded via a vertical or perpendicular magnetic recording technique, for example).

摘要翻译： 在MSN编码形式中，本发明的每个块的符号定义了一个运行的数字和（RDS）值，被定义为RDS（[a]> 1 （1-N-1））= - Sigma（i-1）其中符号a < SUB> i 属于集合{0,1}，并且对于从0到N-1的i的值扩展。 编码器被配置为满足以下特征中的至少一个：a）具有给定长度（L）的符号块用于编码，其中RDS = RDS <0> + 4K，其中K 是整数，RDS是所述运行的数字和，对于所述长度（L）的偶数值，RDS <0> <0>定义为零，而对于所述长度（L）的奇数值而言，RDS < ）具有给定长度（L）的符号块用于MSN编码，并且通过选择编码块来实现编码，使得该组运行数字和（RDS）值是具有满足所需速率的元素的最小数量的集合 值，定义为输入块的长度与输出块的长度之间的比率。 具有简化网格结构的解码器被用于解码（例如在解码从通过垂直或垂直磁记录技术记录了所述信号的介质读取的数字信号时）。

公开(公告)号：US07379516B2

公开(公告)日：2008-05-27

申请号：US10189348

申请日：2002-07-02

申请人： Angelo Dati ,  Filippo Brenna ,  Davide Giovenzana

发明人： Angelo Dati ,  Filippo Brenna ,  Davide Giovenzana

IPC分类号： H04B1/10 ,  H03K5/159

CPC分类号： G11B20/1876 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009

摘要： A receiver in a data read channel has an input terminal for receiving an input signal provided by a transmitter of the data read channel, and produces an output signal at an output terminal. The receiver includes a finite impulse response (FIR) filter coupled to the input terminal and having filter coefficients capable of being adapted, an interpolated timing-recovery circuit coupled to an output of the FIR filter, the timing-recovery circuit having an output signal coupled to the output terminal of the receiver, and a timer circuit coupled to the output terminal and feedback connected to the timing-recovery circuit, wherein the coefficients of the timing-recovery circuit are dynamically adapted using a cost weighted function through a signal power spectrum of the data read channel.

摘要翻译： 数据读通道中的接收器具有用于接收由数据读通道的发送器提供的输入信号的输入端，并在输出端产生输出信号。 接收机包括耦合到输入端并具有能够适配的滤波器系数的有限脉冲响应（FIR）滤波器，耦合到FIR滤波器的输出的内插定时恢复电路，该定时恢复电路具有耦合的输出信号 耦合到所述输出端子的定时器电路和连接到所述定时恢复电路的反馈，其中所述定时恢复电路的系数通过成本加权函数通过信号功率谱进行动态调整，所述信号功率谱是 数据读取通道。

公开(公告)号：US07295764B2

公开(公告)日：2007-11-13

申请号：US10177729

申请日：2002-06-20

申请人： Giorgio Betti ,  Angelo Dati ,  Viviana D'Alto ,  Danilo Pau ,  Filippo Santinello

发明人： Giorgio Betti ,  Angelo Dati ,  Viviana D'Alto ,  Danilo Pau ,  Filippo Santinello

IPC分类号： H04N7/26

CPC分类号： H04N19/00266 ,  H04N19/157 ,  H04N19/172 ,  H04N19/61

摘要： A method of storing a data file, particularly in the MPEG format and including a flow of different frames, comprises a protection system for the data file based on a parameter stored in the data file. Advantageously, the storage method comprises selectively protecting the frames by storing parameters that are associated with corresponding different frames whose values are selected to provide a playing quality level requested by an end user. Also, a method is provided for decoding a data file, particularly of the MPEG type and including a flow of different frames, wherein the data file is stored per above.

摘要翻译： 特别是以MPEG格式存储并包括不同帧流的数据文件的方法包括基于存储在数据文件中的参数的数据文件的保护系统。 有利地，存储方法包括通过存储与其值被选择的相应不同帧相关联的参数来选择性地保护帧，以提供终端用户请求的播放质量等级。 此外，提供了一种用于对数据文件进行解码的方法，特别是MPEG类型的数据文件，并且包括不同帧的流程，其中数据文件存储在上面。

公开(公告)号：US6014613A

公开(公告)日：2000-01-11

申请号：US135963

申请日：1998-08-18

申请人： Angelo Dati ,  Ivan Bietti

发明人： Angelo Dati ,  Ivan Bietti

IPC分类号： H03M1/12 ,  G05B5/01 ,  G05B21/02 ,  H03L7/06 ,  G05B11/42

CPC分类号： G05B5/01 ,  G05B21/02

摘要： A control signal compensation method is particularly intended for an analog/digital processing system provided with a control loop, including in turn a controller and a monitoring circuit. The method includes storing corrections made by the controller, fast processing such as corrections before transmitting the corrections throughout the control loop, and generating a compensation signal for the latency effects of the controller, by the use of a negative feedback loop provided at the monitoring circuit level. A compensation control system implements the above method, and an analog/digital processing system incorporates such a compensation control system

摘要翻译： 控制信号补偿方法特别适用于具有控制回路的模拟/数字处理系统，其中包括控制器和监控电路。 该方法包括存储由控制器进行的校正，在整个控制环路中发送校正之前进行诸如修正之类的快速处理，以及通过使用在监控电路上提供的负反馈回路来产生用于控制器的等待时间效应的补偿信号 水平。 补偿控制系统实现上述方法，并且模拟/数字处理系统结合了这种补偿控制系统

公开(公告)号：US07280295B2

公开(公告)日：2007-10-09

申请号：US11137946

申请日：2005-05-26

申请人： Angelo Dati ,  Augusto Andrea Rossi ,  Davide Giovenzana

发明人： Angelo Dati ,  Augusto Andrea Rossi ,  Davide Giovenzana

IPC分类号： G11B5/09

CPC分类号： G11B27/3027 ,  G11B2220/20

摘要： A method for storing user data on a hard disk drive system comprises distributing user data across a plurality of independent data sectors, with each data sector including a first header having a first preamble field and a first sync mark field, and a second header having a second preamble field and a second sync mark field. The method performs a first timing recovery phase for recovering signal amplitude by acquiring phase and frequency lock from at least one of the preamble fields, and performs a subsequent frame synchronous detection phase by acquiring a corresponding sync mark field.

摘要翻译： 一种用于在硬盘驱动器系统上存储用户数据的方法包括在多个独立数据扇区之间分配用户数据，每个数据扇区包括具有第一前同步码字段和第一同步标记字段的第一标题，以及具有 第二前同步码字段和第二同步标记字段。 该方法通过从前导字段中的至少一个获取相位和频率锁定来执行用于恢复信号幅度的第一定时恢复阶段，并且通过获取对应的同步标记字段来执行后续的帧同步检测阶段。

公开(公告)号：US20060171049A1

公开(公告)日：2006-08-03

申请号：US11397175

申请日：2006-04-04

申请人： Angelo Dati ,  Cecilia Tonci ,  Paolo Gaducci

发明人： Angelo Dati ,  Cecilia Tonci ,  Paolo Gaducci

IPC分类号： G11B5/09

CPC分类号： G11B20/10009

摘要： A method is provided for optimizing a PRML (Partial Response Maximum Likelihood) receiving channel for mass memory data receiving systems comprising an input receiving channel, a receiver placed downstream of the channel, a detector connected in cascade to the receiver, and a summing node being input both the receiver output through a delay line, and the output from the detector through an impulsive filter. The method includes performing an indirect estimate of the noise strength by filtering out the error sequence, i.e. the output signal from the summing node, through a filter, and selecting either the output from the summing node or the output from the filter to obtain an optimization parameter for feedback to the receiving system.

公开(公告)号：US20050264907A1

公开(公告)日：2005-12-01

申请号：US11137946

申请日：2005-05-26

申请人： Angelo Dati ,  Augusto Rossi ,  Davide Giovenzana

发明人： Angelo Dati ,  Augusto Rossi ,  Davide Giovenzana

IPC分类号： G11B27/30 ,  G11B5/09

CPC分类号： G11B27/3027 ,  G11B2220/20

摘要： A method for storing user data on a hard disk drive system comprises distributing user data across a plurality of independent data sectors, with each data sector including a first header having a first preamble field and a first sync mark field, and a second header having a second preamble field and a second sync mark field. The method performs a first timing recovery phase for recovering signal amplitude by acquiring phase and frequency lock from at least one of the preamble fields, and performs a subsequent frame synchronous detection phase by acquiring a corresponding sync mark field.

摘要翻译： 一种用于在硬盘驱动器系统上存储用户数据的方法包括在多个独立数据扇区之间分配用户数据，每个数据扇区包括具有第一前同步码字段和第一同步标记字段的第一标题，以及具有 第二前同步码字段和第二同步标记字段。 该方法通过从前导字段中的至少一个获取相位和频率锁定来执行用于恢复信号幅度的第一定时恢复阶段，并且通过获取对应的同步标记字段来执行后续的帧同步检测阶段。

公开(公告)号：US20050246614A1

公开(公告)日：2005-11-03

申请号：US11025769

申请日：2004-12-20

申请人： Angelo Dati ,  Pierandrea Savo ,  Ezio Iacazio ,  Kelly Fitzpatrick ,  Peter McEwen ,  Bahjat Zafer ,  John McEwen

发明人： Angelo Dati ,  Pierandrea Savo ,  Ezio Iacazio ,  Kelly Fitzpatrick ,  Peter McEwen ,  Bahjat Zafer ,  John McEwen

IPC分类号： G11B20/10 ,  H03M13/03

CPC分类号： G11B20/10009

摘要： A method for detecting signals affected by intersymbol interference provides for a path memory being arranged in the form of a trellis admitting survivor paths comprising a first and a second stage. The first stage includes a shift register exchange with a given number of states and a given length λ. At time k-λ, where λ is said given length, the first stage outputs a) a first state SAkk-λ on the survivor path for the best state Ak at time k, while keeping track of the parity for the state at time k-λ for each of the survivor paths in said path memory, and b) a second state SBkk-λ on the survivor path for another state Bk having the same intersymbol interference state as said best state Ak and the opposite priority state. The second stage as is a two-state shift register exchange having a respective memory length Λ, including respective first and second registers. In said respective first and second registers the survivor paths are stored leading to a respective first σ0k and second (σ1k state, the first respective state being equal to said first state SAkk-λ on said best path, whereby the respective first register contains the backend of said best survivor path, while the respective second register contains the backend of an alternative survivor path, the alternative survivor path being for the state at time k with the same intersymbol interference state as said best state and the opposite parity state.

摘要翻译： 用于检测受码间干扰影响的信号的方法提供了以包含第一和第二阶段的幸存路径的格状形式布置的路径存储器。 第一级包括具有给定数量的状态和给定长度λ的移位寄存器交换。 在时间k-lambda，其中λ表示给定长度，第一级输出a）在幸存路径上的最佳状态A的第一状态S k-λ 并且在所述路径存储器中的每个幸存路径的时间k-λ处跟踪奇偶校验的奇偶校验，以及b）第二状态S B S， 对于具有与所述最佳状态A 相同的符号间干扰状态的另一状态B 的幸存路径上的SUP>＆lt; k-lambda＆lt; 优先状态。 第二级是具有相应存储器长度Lambda的双态移位寄存器交换机，包括相应的第一和第二寄存器。 在所述相应的第一和第二寄存器中存储幸存路径，导致相应的第一西格尔和/或第二（sigma） 状态，所述第一相应状态等于所述最佳路径上的所述第一状态，所述第一寄存器包含所述第一寄存器的后端， 最佳幸存者路径，而相应的第二寄存器包含备用幸存路径的后端，替代的幸存路径用于处于与所述最佳状态和相反奇偶校验状态相同的符号间干扰状态的时间k的状态。