公开(公告)号：US08954650B2

公开(公告)日：2015-02-10

申请号：US13234446

申请日：2011-09-16

Applicant: Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

Inventor： Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/04 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/3422

Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.

Abstract translation: 描述了用于改善非易失性存储器（NVM）的读取耐久性的装置，系统和方法。 该方法包括：确定对应于NVM块的读取计数; 识别NVM的块是否是部分编程块（PPB）; 当识别出块是PPB时，将读取计数与第一阈值进行比较; 并且当另外标识时，将读取计数与第二阈值进行比较，其中第一阈值小于第二阈值。 该方法还包括：识别作为PPB的块; 确定对应于PPB的未编程页面的第一字线; 以及将所述第一字线发送到所述NVM，其中所述NVM应用：对应于所述PPB的未编程页面的字线的第一读取电压电平和对应于所述PPB的编程页面的字线的第二读取电压电平 PPB。

公开(公告)号：US07966456B2

公开(公告)日：2011-06-21

申请号：US11863770

申请日：2007-09-28

Applicant: Sanjeev N. Trika ,  Rick Mangold ,  Andrew Vogan

Inventor： Sanjeev N. Trika ,  Rick Mangold ,  Andrew Vogan

IPC: G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0866 ,  G06F2212/1036 ,  G06F2212/2022

Abstract: Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk.

Abstract translation: 公开了一种减少写回非易失性高速缓冲存储器中的写入次数的方法。 该方法包括：在高速缓冲存储器中写入多个数据，其中高速缓存行用于多个数据中的每一个的元数据被标记为脏; 确定要刷新到硬盘的高速缓冲存储器中的多个数据的数据集，其中硬盘可操作地耦合到高速缓冲存储器; 从所述高速缓存存储器将所述多个数据的数据集合刷新到所述硬盘; 以及向所述高速缓存存储器中写入干净标记，其指定所述多个数据中的哪一个已刷新到所述盘。

公开(公告)号：US20070143536A1

公开(公告)日：2007-06-21

申请号：US11353274

申请日：2006-02-13

Applicant: Jasbir Sidhu ,  Andrew Vogan

Inventor： Jasbir Sidhu ,  Andrew Vogan

IPC: G06F12/00

CPC classification number: G06F3/0656 ,  G06F3/0611 ,  G06F3/0676

Abstract: A data storage device includes a data storage media, a head, a data fetch buffer, and a controller. The head is configured to read data stored in logical block addresses (LBA) on the media. The data fetch buffer is configured to store data. The controller is configured to read data through the head from LBAs on the media that are identified by LBA access sequence information in the data storage device which identifies a sequence of LBAs that a host device will access and to store the read data in the data fetch buffer. The controller is also configured to respond to a read command from the host device that is directed to data at a LBA of the media that is identified the LBA access sequence information and which has been read into the data fetch buffer by communicating the data associated with the read command from the data fetch buffer to the host device.

Abstract translation: 数据存储装置包括数据存储介质，磁头，数据获取缓冲器和控制器。 头部被配置为读取存储在介质上的逻辑块地址（LBA）中的数据。 数据提取缓冲区被配置为存储数据。 控制器被配置为通过头部从数据存储设备中的LBA访问序列信息标识的介质上的LBA读取数据，其标识主机设备将访问的LBA序列并将读取的数据存储在数据获取中 缓冲。 控制器还被配置为响应来自主机设备的读取命令，该命令被指向在标识LBA访问序列信息的媒体的LBA处的数据，并且已经通过传送与数据获取缓冲器相关联的数据而被读取到数据获取缓冲器 读取命令从数据获取缓冲区到主机设备。

公开(公告)号：US20130073786A1

公开(公告)日：2013-03-21

申请号：US13234446

申请日：2011-09-16

Applicant: Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

Inventor： Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/3422

Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.

Abstract translation: 描述了用于改善非易失性存储器（NVM）的读取耐久性的装置，系统和方法。 该方法包括：确定对应于NVM块的读取计数; 识别NVM的块是否是部分编程块（PPB）; 当识别出块是PPB时，将读取计数与第一阈值进行比较; 并且当另外标识时，将读取计数与第二阈值进行比较，其中第一阈值小于第二阈值。 该方法还包括：识别作为PPB的块; 确定对应于PPB的未编程页面的第一字线; 以及将所述第一字线发送到所述NVM，其中所述NVM应用：对应于所述PPB的未编程页面的字线的第一读取电压电平和对应于所述PPB的编程页面的字线的第二读取电压电平 PPB。

公开(公告)号：US20110035534A1

公开(公告)日：2011-02-10

申请号：US12462695

申请日：2009-08-07

Applicant: Andrew Vogan

Inventor： Andrew Vogan

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space.

Abstract translation: 公开了一种设备，系统和方法。 在一个实施例中，该设备包括用于存储多个存储元件的非易失性存储器（NVM）存储阵列。 该设备还包括具有背景空间和前景空间的双目录目录结构。 该结构能够存储几个条目，每个条目对应于存储存储元件的NVM存储阵列中的位置。 背景空间包括写入数组的存储元素的条目，而不会在后台空间中先前存储的存储元素的任何部分覆盖。 前景空间包括用于写入阵列的存储元件的条目，其中至少一次部分覆盖在背景空间中的一个或多个先前存储的存储元件。

公开(公告)号：US20090044078A1

公开(公告)日：2009-02-12

申请号：US11835878

申请日：2007-08-08

Applicant: Andrew Vogan ,  Jawad B. Khan ,  Sowmiya Jayachandran

Inventor： Andrew Vogan ,  Jawad B. Khan ,  Sowmiya Jayachandran

IPC: G06F11/16 ,  H03M13/15

CPC classification number: G11B20/18 ,  G06F11/108 ,  G11B20/10527 ,  G11B2020/1062

Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

Abstract translation: 多通道存储设备可以包括主机控制器，以从主机设备和缓冲存储器接收输入数据，以在下游存储之前存储输入数据和相关联的纠错数据。 缓冲存储器下游的多个存储通道可以将输入数据和相关联的纠错数据存储在非易失性存储介质上的至少一个存储通道中。 主机控制器和缓冲存储器之间的纠错引擎可以对来自主机设备的输入数据执行纠错编码，以产生相关联的纠错数据以存储在缓冲存储器中。 这种纠错引擎可以防止缓冲存储器和存储信道中的数据错误。

公开(公告)号：US08001444B2

公开(公告)日：2011-08-16

申请号：US11835878

申请日：2007-08-08

Applicant: Andrew Vogan ,  Jawad B. Khan ,  Sowmiya Jayachandran

Inventor： Andrew Vogan ,  Jawad B. Khan ,  Sowmiya Jayachandran

IPC: G11C29/00

CPC classification number: G11B20/18 ,  G06F11/108 ,  G11B20/10527 ,  G11B2020/1062

Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

Abstract translation: 多通道存储设备可以包括主机控制器，以从主机设备和缓冲存储器接收输入数据，以在下游存储之前存储输入数据和相关联的纠错数据。 缓冲存储器下游的多个存储通道可以将输入数据和相关联的纠错数据存储在非易失性存储介质上的至少一个存储通道中。 主机控制器和缓冲存储器之间的纠错引擎可以对来自主机设备的输入数据执行纠错编码，以产生相关联的纠错数据以存储在缓冲存储器中。 这种纠错引擎可以防止缓冲存储器和存储信道中的数据错误。

公开(公告)号：US20090089508A1

公开(公告)日：2009-04-02

申请号：US11863770

申请日：2007-09-28

Applicant: Sanjeev N. Trika ,  Rick Mangold ,  Andrew Vogan

Inventor： Sanjeev N. Trika ,  Rick Mangold ,  Andrew Vogan

IPC: G06F13/00

CPC classification number: G06F12/0804 ,  G06F12/0866 ,  G06F2212/1036 ,  G06F2212/2022

Abstract: Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk.

Abstract translation: 公开了一种减少写回非易失性高速缓冲存储器中的写入次数的方法。 该方法包括：在高速缓冲存储器中写入多个数据，其中高速缓存行用于多个数据中的每一个的元数据被标记为脏; 确定要刷新到硬盘的高速缓冲存储器中的多个数据的数据集，其中硬盘可操作地耦合到高速缓冲存储器; 从所述高速缓存存储器将所述多个数据的数据集合刷新到所述硬盘; 以及向所述高速缓存存储器中写入干净标记，其指定所述多个数据中的哪一个已刷新到所述盘。

公开(公告)号：US07345837B1

公开(公告)日：2008-03-18

申请号：US11184273

申请日：2005-07-19

Applicant: Erhard Schreck ,  Donald Brunnett ,  Hung V. Nguyen ,  Bruce Schardt ,  Andrew Vogan

Inventor： Erhard Schreck ,  Donald Brunnett ,  Hung V. Nguyen ,  Bruce Schardt ,  Andrew Vogan

IPC: G11B27/36 ,  G11B5/09

CPC classification number: G11B5/09

Abstract: A disk drive includes a rotatable data storage disk, a transducer, an actuator, and a controller. The transducer is configured to read and write data on the disk. The actuator is configured to position the transducer relative to defined portions of the disk. The controller is configured to determine how many times data has been written to the defined portions of the disk. The controller is also configured to refresh data residing at a particular one of the defined portions of the disk when the number of times data has been written to the particular defined portion of the disk satisfies a threshold value.

Abstract translation: 磁盘驱动器包括可旋转数据存储盘，换能器，致动器和控制器。 传感器配置为在磁盘上读取和写入数据。 致动器被配置成相对于盘的限定部分定位换能器。 控制器被配置为确定数据被写入磁盘的定义部分的次数。 当数据已被写入盘的特定定义部分的次数满足阈值时，控制器还被配置为刷新驻留在盘的特定一个定义部分的数据。

公开(公告)号：US07065613B1

公开(公告)日：2006-06-20

申请号：US10457080

申请日：2003-06-06

Applicant: Lance Flake ,  Andrew Vogan

Inventor： Lance Flake ,  Andrew Vogan

IPC: G06F12/00

CPC classification number: G06F12/0875 ,  G06F12/0804

Abstract: The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to main memory when the old line data represents a currently unused area of the cache. In another embodiment, the invention prevents reading previous line data for a new tag from main memory when the new tag represents a currently unused area of the cache.

Abstract translation: 本发明涉及有效的堆栈高速缓存逻辑，其减少对主存储器的访问次数。 更具体地，在一个实施例中，当旧行数据表示高速缓存的当前未使用区域时，本发明防止将旧行数据写入主存储器。 在另一实施例中，当新标签表示高速缓存的当前未使用区域时，本发明防止从主存储器读取新标签的前一行数据。