摘要:
An optical transceiver includes an optical IC coupled to a processor IC. For transmit, the optical IC can be understood as a transmitter IC including a laser device or array. For receive, the optical IC can be understood as a receiver IC including a photodetector/photodiode device or array. For a transmitter IC, the processor IC includes a driver for a laser of the transmitter IC. The driver includes an equalizer that applies high frequency gain to a signal transmitted with the laser device. For a receiver IC, the processor IC includes a front end circuit to interface with a photodetector of the receiver IC. The front end circuit includes an equalizer that applies high frequency gain to a signal received by the receiver IC. The driver can be configurable to receive a laser having either orientation: ground termination or supply termination.
摘要:
Methods, apparatus and systems for implementing Physical Media Attachment (PMA) alignment and rapid transition from a link training mode to a data mode for next-generation high-speed Ethernet links including a 100 Gbps Ethernet link. Training frames are transmitted between first and second Ethernet interfaces on opposing ends of the link in a pair-wise manner, with a first training frame being sent from a first Ethernet interface and a second training frame being returned from the second Ethernet interface. The training frames have a length that is different that the length of Physical Media Attachment (PMA) frames, and the returned training frames include receiver readiness status indicia identifying a readiness status of a local receiver port, frame alignment offset data identifying a relative offset between a training frame and a predetermined location in a PMA frame, and countdown data. The readiness status indicia, frame alignment offset data and countdown data are employed to facilitate a rapid transition from the link training mode to the data mode.
摘要:
Technologies for autonegotiation of communications operational modes over copper cable include a network port logic having a communication link coupled to a remote link partner. The network port logic may start an autonegotiation protocol upon reset, when the link is broken, or upon manual renegotiation. The network port logic transmits an autonegotiation page to the remote link partner that indicates single-lane communications ability over copper cable. The network port logic receives an autonegotiation page from the link partner indicating single-lane communications ability over copper cable. If the network port logic and link partner have a common single-lane communication ability, the link may be activated. The autonegotiation pages may be base pages or next pages. The single-lane communication ability may be indicated by one or more bits of the autonegotation pages. The link may be established at 1 gigabit or 10 gigabits per second. Other embodiments are described and claimed.
摘要:
Methods, apparatus and systems for implementing link training for next-generation high-speed Ethernet links including a 100 Gbps Ethernet link. Training frames are transmitted from a transmit port to be received at a receive port, with each training frame comprising a frame marker portion, a control channel portion, and a training pattern portion. Four-level signaling including a low level signal, first and second intermediate level signals, and a high level signal is implemented for the training pattern portion of the training frame using a pseudo-random bit pattern, while only the low and high level signals are employed for the frame marker and control channel portions of the training frame. The four-level signaling may employ PAM4 encoding. Examples of apparatus and systems in which the link training techniques may be implemented include blade servers and network routers and switches.
摘要:
Technologies for transmitter equalization in a communication system include reading local transmitter equalization settings from a transmitter equalization register of a first communication device and writing the local transmitter equalization settings to a transmitter equalization register of a second communication device communicatively coupled with the first communication device via a chip-to-chip communication link. Additionally, requested transmitter equalization settings may be read from the transmitter equalization register of the second communication device and written to the transmitter equalization register of the first communication device. The reading and writing process may be repeated for the opposite communication direction and for other communication lane interfaces of the first and second communication devices.
摘要:
A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device.
摘要:
Methods, apparatus and systems for implementing link training for next-generation high-speed Ethernet links including a 100 Gbps Ethernet link. Training frames are transmitted from a transmit port to be received at a receive port, with each training frame comprising a frame marker portion, a control channel portion, and a training pattern portion. Four-level signaling including a low level signal, first and second intermediate level signals, and a high level signal is implemented for the training pattern portion of the training frame using a pseudo-random bit pattern, while only the low and high level signals are employed for the frame marker and control channel portions of the training frame. The four-level signaling may employ PAM4 encoding. Examples of apparatus and systems in which the link training techniques may be implemented include blade servers and network routers and switches.
摘要:
Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. In accordance with one aspect, embodiments are disclosed that facilitate assessing the probability of error bursts in receivers that include decision feedback equalizers (DFEs) and that perform non-contiguous mapping of received bits to frame bits. From this probability, calculation of a mean-time to false packet acceptance (MTTFPA) may be determined, and indication that a projected link MTTFPA is too low can be used to trigger an alert or invoke some safety mechanism. Associated operations may then be performed to ensure the link is prevented from being operated in an unsafe condition under which false packet acceptance may occur.
摘要:
Methods and test equipment for measuring jitter in a Pulse Amplitude Modulated (PAM) transmitter. Under one procedure, a first two-level PAM signal test pattern is used to measure clock-related jitter separated into random and deterministic components, while a second two-level PAM signal test pattern is used to measure oven-odd jitter (EOJ). Under another procedure, A four-level PAM signal test pattern is used to measure jitter-induced noise using distortion analysis. Test equipment are also disclosed for implementing various aspects of the test methods.
摘要:
Methods, apparatus and systems for de-correlating training pattern sequences for high-speed links and interconnects. The high-speed links and interconnects employs multiple lanes in each direction for transmitting and receiving data, and may be physically implemented via signal paths in an inter-plane board such as a backplane or mid-plane, or via a cable. During link training, a training pattern comprising a pseudo random bit sequence (PBRS) is sent over each lane. The PBRS for each lane is generated by a PBRS generator based on a PRBS polynomial that is unique to that lane. Since each lane employs a different PRBS polynomial, the training patterns between lanes are substantially de-correlated. Link negotiation may be performed between link endpoints to ensure that the PBRS polynomials used for all of the lanes in the high-speed link or interconnect are unique. Exemplary uses include Ethernet links, Infiniband links, and multi-lane serial interconnects.