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公开(公告)号：US12063034B2
公开(公告)日：2024-08-13
申请号：US17823401
申请日：2022-08-30
申请人： KANDOU LABS SA
发明人： Armin Tajalli
IPC分类号： H03K17/687 , H03K19/00 , H04L12/40
CPC分类号： H03K17/6872 , H03K19/0005 , H04L12/40 , H03K2217/0063 , H03K2217/0072
摘要： Methods and systems are described for an output driver composed of complementary metal-oxide semiconductor (CMOS) devices, the output driver having a line driver control stage configured to selectively output a reference voltage or a first supply voltage at the control stage output node in response to a data signal, and a line driver output circuit configured to generate an output signal on a multi-wire bus, wherein the CMOS devices of the line driver output circuit are calibrated to have an on-resistance matched to a termination impedance via first and second supply voltages provided to the line driver control stage and the line driver output circuit, respectively.
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公开(公告)号：US12009919B2
公开(公告)日：2024-06-11
申请号：US18322247
申请日：2023-05-23
申请人： Kandou Labs SA
发明人： Filippo Borlenghi , David Stauffer
CPC分类号： H04L1/0045 , H04L1/0061 , G06F13/4282 , G06F2213/0042
摘要： Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
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公开(公告)号：US20230308065A1
公开(公告)日：2023-09-28
申请号：US17702882
申请日：2022-03-24
申请人： Kandou Labs SA
发明人： Maik Fuhs
CPC分类号： H03G3/30 , H03F3/45264 , H03G2201/103
摘要： Obtaining a bias control signal at a current source and responsively generating a fixed current, receiving a differential voltage input signal at corresponding differential input nodes of a plurality of differential amplifier stages connected to the current source, the plurality of differential amplifier stages comprising a primary amplifier stage and a set of supplemental amplifier stages, each of the plurality of differential amplifier stages having a pair of output nodes connected to common load impedances, generating an amplified differential voltage output signal on the pair of output nodes by directing the fixed current through the load impedances, and selectively connecting each supplemental amplifier stage in parallel to the primary amplifier stage via a corresponding gain control switch of a set of gain control switches connected to the primary amplifier stage and the plurality of supplemental amplifier stages to adjust an overall transconductance of the plurality of differential amplifier stages.
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公开(公告)号：US20230013802A1
公开(公告)日：2023-01-19
申请号：US17937197
申请日：2022-09-30
申请人： KANDOU LABS SA
发明人： Kiarash Gharibdoust , Ali Hormati
摘要： Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.
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公开(公告)号：US11477055B2
公开(公告)日：2022-10-18
申请号：US17341030
申请日：2021-06-07
申请人： Kandou Labs SA
发明人： Ali Hormati
IPC分类号： H01Q13/24 , H04L25/02 , H04L25/49 , H04L25/08 , H04B3/14 , H04L25/14 , H04W72/04 , H04L25/03
摘要： Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
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公开(公告)号：US20220303049A1
公开(公告)日：2022-09-22
申请号：US17834628
申请日：2022-06-07
申请人： Kandou Labs SA
发明人： Filippo Borlenghi , David Stauffer
IPC分类号： H04L1/00
摘要： Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.
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公开(公告)号：US11362800B2
公开(公告)日：2022-06-14
申请号：US16781910
申请日：2020-02-04
申请人： Kandou Labs SA
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.
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公开(公告)号：US11349459B2
公开(公告)日：2022-05-31
申请号：US17210260
申请日：2021-03-23
申请人： Kandou Labs SA
摘要： Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.
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公开(公告)号：US11283654B2
公开(公告)日：2022-03-22
申请号：US17037054
申请日：2020-09-29
申请人： Kandou Labs SA
发明人： Roger Ulrich
IPC分类号： H04L25/03 , H04B3/04 , H03K19/0185 , H03K19/00 , H04L25/49
摘要： A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.
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公开(公告)号：US11265190B2
公开(公告)日：2022-03-01
申请号：US17158980
申请日：2021-01-26
申请人： Kandou Labs SA
发明人： Ali Hormati
摘要： Methods and systems are described for generating a time-varying information signal at an output of a variable gain amplifier (VGA), sampling, using a sampler having a vertical decision threshold associated with a target signal amplitude, the time-varying information signal asynchronously to generate a sequence of decisions from varying sampling instants in sequential signaling intervals, the sequence of decisions comprising (i) positive decisions indicating the time-varying information signal is above the target signal amplitude and (ii) negative decisions indicating the time-varying information signal is below the target signal amplitude, accumulating a ratio of positive decisions to negative decisions, and generating a gain feedback control signal to adjust a gain setting of the VGA responsive to a mismatch of the accumulated ratio with respect to a target ratio.
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