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公开(公告)号：US20230019869A1
公开(公告)日：2023-01-19
申请号：US17812675
申请日：2022-07-14
IPC分类号： H01L23/00 , H01L23/498
摘要： An optically occlusive protective element for bonded structures, embodiments of which disclosed herein relate to directly bonded structures along a bond interface. Specifically, two elements, a semiconductor element and an occlusive element, may be directly bonded to one another without an intervening adhesive along a bonding interface. The semiconductor element includes active circuitry which, after bonding, is protected by the occlusive element. The occlusive element includes several optically occlusive layers which are arranged to inhibit an optical interrogation of the active circuitry. Such layers may further include occlusive strips which may or may not overlap with other occlusive strips from other occlusive layers when the occlusive layers are stacked vertically.
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公开(公告)号：US20230005850A1
公开(公告)日：2023-01-05
申请号：US17809723
申请日：2022-06-29
IPC分类号： H01L23/00 , H01L25/065
摘要： A bonded structure is disclosed. The bonded structure can include a first element that includes a first bonding layer, the first bonding layer that has a first contact pad and a routing trace. The routing trace is formed at the same level as the first contact pad. The bonded structure can include a second element that includes a second bonding layer that has a second contact pad. The first element and the second element are directly bonded such that the first contact pad and the second contact pad are directly bonded without an intervening adhesive
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公开(公告)号：US11462419B2
公开(公告)日：2022-10-04
申请号：US16503021
申请日：2019-07-03
发明人： Belgacem Haba
IPC分类号： H01L21/56 , H01L21/768 , H01L23/31 , H01L21/82 , H01L23/528
摘要： Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.
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公开(公告)号：US20220302048A1
公开(公告)日：2022-09-22
申请号：US17834737
申请日：2022-06-07
发明人： Javier A. DeLaCruz , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L23/00 , H01L21/66 , H01L23/528
摘要： A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
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公开(公告)号：US11373963B2
公开(公告)日：2022-06-28
申请号：US16844941
申请日：2020-04-09
发明人： Javier A. DeLaCruz , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L23/00 , H01L23/528 , H01L21/66
摘要： A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
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公开(公告)号：US20220139849A1
公开(公告)日：2022-05-05
申请号：US17454971
申请日：2021-11-15
发明人： Javier A. DeLaCruz , Rajesh Katkar
IPC分类号： H01L23/00
摘要： A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
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公开(公告)号：US11276676B2
公开(公告)日：2022-03-15
申请号：US16413429
申请日：2019-05-15
发明人： Paul M. Enquist , Belgacem Haba
IPC分类号： H01L25/00 , H01L25/18 , H01L27/146 , H01L21/822 , H01L23/31 , H01L21/768 , H01L23/48 , H01L23/00 , H01L25/07
摘要： Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.
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公开(公告)号：US11257727B2
公开(公告)日：2022-02-22
申请号：US16678037
申请日：2019-11-08
发明人： Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh , Shaowu Huang , Guilian Gao , Ilyas Mohammed
摘要： Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
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公开(公告)号：US11171117B2
公开(公告)日：2021-11-09
申请号：US16438714
申请日：2019-06-12
发明人： Guilian Gao , Belgacem Haba
IPC分类号： H01L25/065 , H01L21/768 , H01L23/48 , H01L25/00 , H01L23/00
摘要： Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.
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公开(公告)号：US20210313225A1
公开(公告)日：2021-10-07
申请号：US17315166
申请日：2021-05-07
IPC分类号： H01L21/768 , H01L23/48 , H01L23/00 , H01L25/065 , H01L25/00 , H01L27/06
摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
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