VALIDATION OF SCHEMA AND SCHEMA CONFORMANCE VERIFICATION

    公开(公告)号:US20170116350A1

    公开(公告)日:2017-04-27

    申请号:US15399004

    申请日:2017-01-05

    IPC分类号: G06F17/30 G06F17/27

    摘要: A schema can be received as an input. For at least one element in the schema, the element can be parsed from the schema. The parsed element can be validated by comparing the parsed element to a node within a first schema parse tree. A parse tree node can be generated for the parsed element. The parse tree node can be configured to call at least one validation rule, external to a second schema parse tree, which validates an element of a document corresponding to the parse tree node. The parse tree node can be added to the second schema parse tree. The second schema parse tree can be output.

    CONSTRAINING FIR FILTER TAPS IN AN ADAPTIVE ARCHITECTURE
    3.
    发明申请
    CONSTRAINING FIR FILTER TAPS IN AN ADAPTIVE ARCHITECTURE 有权
    在自适应建筑中约束FIR滤波器

    公开(公告)号:US20160217820A1

    公开(公告)日:2016-07-28

    申请号:US15087836

    申请日:2016-03-31

    IPC分类号: G11B20/10 G11B5/008

    CPC分类号: G11B20/10046 G11B5/00813

    摘要: According to one embodiment, a system for processing data includes a processor and logic integrated with and/or executable by the processor. The logic is configured to individually set, for each of one or more range-constrained finite impulse response (FIR) filter taps configured for use in a FIR filter, a predetermined range of values suitable for controlling an equalizer response. The logic is also configured to pass data through the equalizer comprising the FIR filter to obtain equalized data. Each of the one or more range-constrained FIR filter taps are individually adaptive within its predetermined range of values. Also, the data is read from a magnetic storage medium.

    摘要翻译: 根据一个实施例,用于处理数据的系统包括与处理器集成和/或可执行的处理器和逻辑。 逻辑被配置为针对被配置为在FIR滤波器中使用的一个或多个范围约束的有限脉冲响应(FIR)滤波器抽头中的每个单独设置适合于控制均衡器响应的预定范围的值。 逻辑还被配置为通过包括FIR滤波器的均衡器传递数据以获得均衡的数据。 一个或多个范围受限的FIR滤波器抽头中的每一个在其预定的值范围内是单独自适应的。 此外,从磁存储介质读取数据。

    SPECULATIVE CHECKIN OF ERAT CACHE ENTRIES
    4.
    发明申请

    公开(公告)号:US20200073816A1

    公开(公告)日:2020-03-05

    申请号:US16117099

    申请日:2018-08-30

    摘要: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.

    RINSING AND DRYING FOR ELECTROCHEMICAL PROCESSING

    公开(公告)号:US20160076167A1

    公开(公告)日:2016-03-17

    申请号:US14948259

    申请日:2015-11-21

    IPC分类号: C25F7/00 C25F3/12

    摘要: An electroplating/etch apparatus including a fluid jet and a dryer present over the tank containing the electrolyte for the electroplating/etch process. The fluid jet and the dryer remove excess liquids, such as electrolyte, from the component being plated or etched, e.g., working electrode. The working electrode is present on a holder that traverses from a first position within the tank during a plating or etch operation to a second position that is outside the containing the plating electrolyte. The fluid jet rinses the working electrode when the holder is in the second position, and the forced air dryer blows any remaining fluid from the fluid jet and the electrolyte from the working electrode into the tank.

    INTEGRATED CIRCUIT CURRENT REGULATOR
    6.
    发明申请
    INTEGRATED CIRCUIT CURRENT REGULATOR 失效
    集成电路电流调节器

    公开(公告)号:US20050248390A1

    公开(公告)日:2005-11-10

    申请号:US10908289

    申请日:2005-05-05

    IPC分类号: G06F1/26

    CPC分类号: G06F1/26

    摘要: An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage. A resistance as a function of supply voltage R(Vdd) characteristic is realized to reduce or eliminate mid-frequency power supply noise, caused by on-chip switching activity variations while minimizing additional on-chip power dissipation.

    摘要翻译: 集成电路电流调节器,其基于集成电路的开关活动来补偿所需电流的变化。 第一实施例包括具有缩放单元的电压控制片上旁路电路,以将输入电压分成n个分数电压,并且片上电压监视器将片上电源电压的一部分与参考电压进行比较,并且控制 相应的片上电源旁路。 每个比较器至少有一个旁路电阻根据相应比较器的输出信号在电源电压和地电位之间切换,以抑制电源噪声。 旁路电阻R的值随着片上电源电压的降低而增加,随着电源电压的增加而减小。 实现了作为电源电压R(Vdd)特性的电阻,以减少或消除由片上开关活动变化引起的中频电源噪声,同时最大限度地减少额外的片上功耗。

    TAPE HEAD AND SYSTEM HAVING ASYMMETRICAL CONSTRUCTION

    公开(公告)号:US20180122408A1

    公开(公告)日:2018-05-03

    申请号:US15789477

    申请日:2017-10-20

    IPC分类号: G11B5/187 G11B5/008 G11B5/48

    摘要: An apparatus according to one embodiment includes a module having a tape bearing surface, a first edge, and a second edge, where a tape tenting region extends from the first edge toward the second edge, the first edge being a first end of the tape tenting region, a second end of the tape tenting region being positioned between the first and second edges. The apparatus includes a guide positioned relative to the first edge for inducing tenting of a moving magnetic recording tape and a transducer positioned in the tape tenting region. In addition, the module has a wear coating on a media facing side of the transducer, where a peak height is defined between the peak of tenting and an upper surface of the coating. The thickness of the wear coating is in a range of between about 0.5 and about 3 times the peak height.