-
公开(公告)号：US5822341A
公开(公告)日：1998-10-13
申请号：US418661
申请日：1995-04-06
申请人： Paul Winterrowd , Torkjell Berge
发明人： Paul Winterrowd , Torkjell Berge
CPC分类号： H03M13/4169 , G11C8/16 , H03M13/41
摘要： A memory block structure for use within a viterbi decoder includes multiple dual port RAMs configured as multiport RAMs. The memory block structure is configured to allow a one-word write operation and an N-word read operation during a single clock cycle in order to achieve one decoded output symbol per clock period using the viterbi algorithm. By using dual port RAMs, a more densely packed and less expensive memory block structure is achieved. An encoded stream of input symbols are input to the viterbi decoder and written to the memory block structure one word at a time. Once X+Y bits have been written to the memory block structure, the decoder will then read N words from the memory block structure, simultaneously, reading back through X+Y words and outputting Y bits N at a time at the end of the trace back through memory. This process is repeated once the next Y words have been written to the memory block 22, with X+Y words being traced back through and the appropriate Y bits being output, until the entire encoded stream of input symbols has been decoded.
摘要翻译： 在维特比解码器中使用的存储器块结构包括配置为多端口RAM的多个双端口RAM。 存储器块结构被配置为在单个时钟周期期间允许一字写入操作和N字读操作，以便使用维特比算法在每个时钟周期内实现一个解码的输出符号。 通过使用双端口RAM，实现了更密集封装和更便宜的存储器块结构。 将输入符号的编码流输入到维特比解码器，并一次写入存储器块结构一个字。 一旦X + Y位被写入存储器块结构，解码器将从存储器块结构中读取N个字，同时通过X + Y个字读回并在跟踪结束时一次输出Y个位N 回忆一下 一旦已经将下一个Y字写入存储器块22，将X + Y个字追溯到正在输出的适当的Y位，直到输入符号的整个编码流被解码为止，这一过程被重复。
-
公开(公告)号：US5428564A
公开(公告)日：1995-06-27
申请号：US924676
申请日：1992-08-03
申请人： Kel D. Winters
发明人： Kel D. Winters
CPC分类号： G11C15/04 , G11C15/043
摘要： A content addressable memory cell includes six transistors connected together to perform memory read, memory write, and matching operations. This cell has the ability to perform typical memory write and memory read operations as well as the capability of signalling whether or not its stored data matches data that is being searched for. A cross-coupling scheme is used in the memory cell so that a high potential will always be stored on the gate of a transistor whose source is at ground. This cross-coupling scheme increases the amount of charge stored on the storage transistor and decreases the required frequency of refresh operations. In addition to the transistors configured to store data, an additional transistor configured as a diode is used as a rapid discharge path to maximize the efficiency of the cell during a read operation. During a match operation another transistor is utilized to discharge the Match line quickly in the event the stored data does not match the data that is being searched for.
摘要翻译： 内容可寻址存储单元包括连接在一起以执行存储器读取，存储器写入和匹配操作的六个晶体管。 该单元能够执行典型的存储器写入和存储器读取操作以及用于发信号通知其存储的数据是否与要搜索的数据相匹配的能力。 在存储器单元中使用交叉耦合方案，使得高电位将始终存储在源极接地的晶体管的栅极上。 这种交叉耦合方案增加存储在存储晶体管上的电荷量，并减少刷新操作的所需频率。 除了配置为存储数据的晶体管之外，将配置为二极管的附加晶体管用作快速放电路径，以在读取操作期间使单元的效率最大化。 在匹配操作期间，在存储的数据与正被搜索的数据不匹配的情况下，利用另一个晶体管来快速放电Match线。
-
3.发明授权Single clock cycle data compressor/decompressor with a string reversal mechanism 失效单时钟周期数据压缩器/解压缩器与字符串反转机制
公开(公告)号：US5818873A
公开(公告)日：1998-10-06
申请号：US924293
申请日：1992-08-03
申请人： Robert Lyle Wall , Kel D. Winters
发明人： Robert Lyle Wall , Kel D. Winters
CPC分类号： G06T9/005 , H03M7/3088
摘要： A single clock cycle adaptive data compressor/decompressor with a string reversal mechanism is described which can perform data compression and decompression at the rate of one uncompressed symbol per clock cycle. The LZW data compression algorithm has been improved for use in this data compressor. The compressor builds a string table as the data is received. Each string within the table is made up of the address within the table of the longest previously seen matching string and the one character that makes this string different. This data compressor/decompressor utilizes a content addressable memory to store the string table. This content addressable memory allows the compressor to store the current symbol string in a table while that same string table is simultaneously searched for the current string. During decompression the characters within a symbol string are output in reverse of the order in which they were input. In order for the data to be restored to its original format the characters within a string must be reversed before they are output. Two dual-ported random-access memories are used as circular queues to perform this string reversal. These dual-ported random-access memories have the capability to output the characters within a string from the string reversal mechanism in the order that they were input. The first dual-ported random access memory is used to store the strings of symbols to be reversed and the second dual-ported random access memory is used to store the addresses of the first and last symbol of each string that is stored in the first dual-ported random-access memory.
摘要翻译： 描述了具有字符串反转机制的单个时钟周期自适应数据压缩器/解压缩器，其可以以每个时钟周期的一个未压缩符号的速率执行数据压缩和解压缩。 LZW数据压缩算法已被改进，用于该数据压缩器。 压缩器在接收到数据时构建一个字符串表。 表中的每个字符串都由最早以前看到的匹配字符串的表中的地址和使此字符串不同的一个字符组成。 该数据压缩器/解压缩器利用内容可寻址存储器来存储字符串表。 该内容可寻址存储器允许压缩器将当前符号串存储在表中，同时搜索当前字符串。 在解压缩期间，符号串中的字符按照输入顺序的顺序输出。 为了使数据恢复到其原始格式，字符串中的字符在输出之前必须相反。 两个双端口随机存取存储器用作循环队列来执行此字符串反转。 这些双端口随机存取存储器具有从字符串反转机制输出串中的字符的能力，以便输入它们的顺序。 第一双端口随机存取存储器用于存储要反转的符号串，并且第二双端口随机存取存储器用于存储存储在第一双端口随机存取存储器的第一双端口随机存取存储器中的每个字符串的第一个和最后一个符号的地址。 - 运行的随机存取存储器。
-
公开(公告)号：US5396502A
公开(公告)日：1995-03-07
申请号：US911153
申请日：1992-07-09
摘要： The present invention is for a Error Correction Unit (ECU) that uses a single stack architecture for the generation, reduction and evaluation of the polynomials involved in the correction of a Reed-Solomon code. The circuit uses the same hardware to generate the syndromes, reduce the .OMEGA.(x) and .LAMBDA.(x) polynomials and evaluate the .OMEGA.(x) and .LAMBDA.(x) polynomials. Some of the specifics involved in calculating and reducing the polynomials mentioned above are novel as well. First, the implementation of the general Galois field multiplier is new and faster than previous implementations. Second, the circuit for implementing the Galois field inverse function has not appeared in prior art designs. Third, a novel method of generating the .OMEGA.(x) and .LAMBDA.(x) polynomials (including alignment of these polynomials prior to evaluation) is utilized. Fourth, corrections are performed in the same order as they are received using a premultiplication step prior to evaluation. Fifth, a novel method of implementing flags for uncorrectable errors is used. Sixth, the ECU is data driven in that nothing happens if no data is present. Finally, interleaved data is handled internally to the chip.
摘要翻译： 本发明涉及一种误差校正单元（ECU），该纠错单元使用单个堆叠架构来生成，减少和评估涉及Reed-Solomon码校正的多项式。 该电路使用相同的硬件来产生综合征，减少OMEGA（x）和LAMBDA（x）多项式，并评估OMEGA（x）和LAMBDA（x）多项式。 计算和减少上述多项式的一些细节也是新颖的。 首先，一般Galois域乘法器的实现是比以前的实现新的和更快的。 其次，用于实现伽罗瓦域反函数的电路在现有技术设计中没有出现。 第三，利用生成OMEGA（x）和LAMBDA（x）多项式（包括评估之前这些多项式的对齐）的新方法。 第四，在评估之前使用预乘步骤以与它们接收的顺序相同的顺序进行校正。 第五，使用了一种用于实现不可校正错误的标志的新方法。 第六，ECU是数据驱动的，因为没有数据存在，没有任何反应。 最后，交织数据在芯片内部处理。
-
公开(公告)号：US5515310A
公开(公告)日：1996-05-07
申请号：US357848
申请日：1994-12-14
申请人： Kel D. Winters
发明人： Kel D. Winters
CPC分类号： G11C15/04 , G11C15/043
摘要： A content addressable memory cell includes six transistors connected together to perform memory read, memory write, and matching operations. This cell has the ability to perform typical memory write and memory read operations as well as the capability of signalling whether or not its stored data matches data that is being searched for. A cross-coupling scheme is used in the memory cell so that a high potential will always be stored on the gate of a transistor whose source is at ground. This cross-coupling scheme increases the amount of charge stored on the storage transistor and decreases the required frequency of refresh operations. In addition to the transistors configured to store data, an additional transistor configured as a diode is used as a rapid discharge path to maximize the efficiency of the cell during a read operation. During a match operation another transistor is utilized to discharge the Match line quickly in the event the stored data does not match the data that is being searched for.
-
-
-
-
搜索结果
5 条记录 (耗时 0.014 秒)
