公开(公告)号：US07870176B2

公开(公告)日：2011-01-11

申请号：US11176149

申请日：2005-07-07

申请人： Doron Solomon ,  Gilad Garon

发明人： Doron Solomon ,  Gilad Garon

IPC分类号： G06F17/14

CPC分类号： H03M13/4169 ,  G06F17/142 ,  H03M13/1105 ,  H03M13/2957 ,  H03M13/39 ,  H03M13/3966 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/4146 ,  H03M13/6508 ,  H03M13/6511 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6561

摘要： A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising: a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said computation unit for the one stage so that only one computation unit is required for the stage; and a controller configured and arranged so as to provide coefficients to the computational unit, and control the sizes of memory and multiplexing architecture in the storage unit; wherein the multipliers' coefficients, the coefficients of the computational unit, the sizes of memories, and multiplexing architecture, for each stage are modified as a function of the value of N. The architecture can be implemented as an integrated chip, and used in communication devices.

摘要翻译： 一种用于执行多级向量的快速正交变换的可重构架构和方法，所述向量的大小为N，其中N可以变化，并且级数是N的函数，所述架构包括：计算单元，其被配置和 布置成包括一个或多个蝴蝶单元; 包括耦合到所述计算单元的输出的一个或多个乘法器的块，被配置和布置成为所述变换的至少一个阶段执行所有蝴蝶计算; 存储单元，被配置和布置为存储蝶形计算的中间结果和预定系数，供计算单元用于执行每个蝶式运算，该存储单元包括存储器和复用结构; 所述存储单元包括存储器和复用架构; 多路复用器单元，其被配置和布置为使用所述一级的所述计算单元对所述变换的所有蝶式计算进行时间复用，使得仅需要一个计算单元用于所述级; 以及控制器，其被配置和布置为向所述计算单元提供系数，并且控制所述存储单元中的存储器和复用架构的大小; 其中每个级的乘法器系数，计算单元的系数，存储器的大小和复用架构被修改为N的值的函数。架构可以被实现为集成芯片，并且用于通信 设备。

公开(公告)号：US07568059B2

公开(公告)日：2009-07-28

申请号：US11071340

申请日：2005-03-03

申请人： Doron Solomon ,  Gilad Garon

发明人： Doron Solomon ,  Gilad Garon

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F9/44505 ,  G06F13/4022 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

摘要翻译： 公开了一种用于处理根据由一系列算法定义的多个通信协议中的任何一个编码的信号的芯片架构。 芯片架构包括多个宏功能，每个巨型功能以可重用的可重新配置功能块的形式，用于实现实现每个通信协议的物理层所必需的不同算法; 以及多个开关，被配置为响应选择的控制信号，以便互连所需的宏功能，以处理用每个协议编码的信号。 优选地，使用两个或多个协议的算法来使用至少一些相同的宏功能。

公开(公告)号：US20220337973A1

公开(公告)日：2022-10-20

申请号：US17659051

申请日：2022-04-13

申请人： ASOCS Ltd.

发明人： Vitaly Lutsky

IPC分类号： H04W4/029 ,  H04W56/00 ,  G01S5/02

摘要： Systems, methods, and software can provide high-accuracy position estimation for mobile user equipment (UE) configured for use within a service area covered by a plurality of radio units, e.g., O-RUs, with known position including coordinates. A channel estimate can be derived for a channel between a given UE and each of a plurality of radio units based on a sounding reference signal (SRS) received from the UE and used to select a subset of the radio units. The shortest delay can be calculated for the given UE to each O-RU in the subset, forming a set of uplink-time-difference-of-arrival (UL-TDOA) measurements; position of the given UE in the service area can be estimated based on the UL-TDOA measurements. The O-RU synchronization error can be estimated for each O-RU in the subset using estimated positions of the given UE and corresponding UL-TDOA measurements.

公开(公告)号：US09448963B2

公开(公告)日：2016-09-20

申请号：US12490221

申请日：2009-06-23

申请人： Doron Solomon ,  Gilad Garon

发明人： Doron Solomon ,  Gilad Garon

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F15/78

CPC分类号： G06F9/44505 ,  G06F13/4022 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.

公开(公告)号：US11539115B2

公开(公告)日：2022-12-27

申请号：US17092885

申请日：2020-11-09

申请人： ASOCS Ltd.

发明人： Gabriel Guri

IPC分类号： H01Q1/24 ,  H04B7/024

摘要： Distributed antenna systems (DAS) and methods are disclosed that are aware of cellular user/antenna relationships. The DAS systems and/or methods include or use one or more User Aware Units that provide the functionality of knowing (or, knowledge of) which cellular user(s) each antenna can communicate with (and vice versa). The User Aware Unit functions to gather information about the reception in each antenna in order to identify the cellular users that the respective antenna can communicate with or best communicate with compared to other cellular users.

公开(公告)号：US20210057802A1

公开(公告)日：2021-02-25

申请号：US17092885

申请日：2020-11-09

申请人： ASOCS Ltd.

发明人： Gabriel Guri

IPC分类号： H01Q1/24 ,  H04B7/024

摘要： Distributed antenna systems (DAS) and methods are disclosed that are aware of cellular user/antenna relationships. The DAS systems and/or methods include or use one or more User Aware Units that provide the functionality of knowing (or, knowledge of) which cellular user(s) each antenna can communicate with (and vice versa). The User Aware Unit functions to gather information about the reception in each antenna in order to identify the cellular users that the respective antenna can communicate with or best communicate with compared to other cellular users.

公开(公告)号：US10834729B1

公开(公告)日：2020-11-10

申请号：US16374591

申请日：2019-04-03

申请人： ASOCS Ltd.

发明人： Gabriel Guri

IPC分类号： H04W72/04 ,  H04W72/08 ,  H04L5/00 ,  H01Q1/24 ,  H04W88/08

摘要： Distributed antenna systems (DAS) and methods are disclosed that are aware of cellular user/antenna relationships. The DAS systems and/or methods include or use one or more User Aware Units that provide the functionality of knowing (or, knowledge of) which cellular user(s) each antenna can communicate with (and vice versa). The User Aware Unit functions to gather information about the reception in each antenna in order to identify the cellular users that the respective antenna can communicate with or best communicate with compared to other cellular users.

公开(公告)号：US07908542B2

公开(公告)日：2011-03-15

申请号：US11210621

申请日：2005-08-24

申请人： Doron Solomon ,  Gilad Garon

发明人： Doron Solomon ,  Gilad Garon

IPC分类号： H03M13/00

CPC分类号： H03M13/4107 ,  H03M13/41 ,  H03M13/4161 ,  H03M13/4169 ,  H03M13/6502 ,  H03M13/6513 ,  H03M13/6561

摘要： A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non-recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks, BMU generators and trace-back mechanisms for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.

摘要翻译： 描述了一种芯片架构核心，用于根据一个或多个不同大小和约束K的递归和/或非递归系统网格码以及生成多项式对由核心接收的一个或多个向量进行解码。 核心包括：解码器，包括（a）ACS块的可重新配置网络，用于递归和非递归系统形式的BMU发生器和追溯机制，以及（b）ACS块，BMU发生器和跟踪 - 反向机制被布置成使得网络组件的精确数量可以在网络中被连续重新排列和互连，作为大小的函数，以及用于对由核心接收的矢量进行编码的每个代码的约束K和生成多项式。

公开(公告)号：US20090240855A1

公开(公告)日：2009-09-24

申请号：US12413012

申请日：2009-03-27

申请人： Gaby Guri ,  Doron Solomon

发明人： Gaby Guri ,  Doron Solomon

IPC分类号： G06F13/42

CPC分类号： G06F17/5045

摘要： An apparatus and method for control in a reconfigurable architecture is shown and described. In one example, an integrated circuit configured to implement a plurality of communications standards includes a plurality of upper level controllers and a plurality of lower level controllers. The upper level controller are configured to operate according to a portion of a communications standard and implement upper level control functions for the associated standard. The low level controllers are capable of communicating with each of the upper level controllers and can be assigned to each of the upper level controls to implement low level functions of each of the plurality of communications standards.

摘要翻译： 显示和描述了可重构架构中的控制装置和方法。 在一个示例中，被配置为实现多个通信标准的集成电路包括多个上层控制器和多个下层控制器。 上级控制器被配置为根据通信标准的一部分进行操作，并实现相关标准的上级控制功能。 低级别控制器能够与每个上级控制器通信，并且可以分配给每个上级控制以实现多个通信标准中的每一个的低级功能。