公开(公告)号：US20010014959A1

公开(公告)日：2001-08-16

申请号：US09745523

申请日：2000-12-21

Inventor： Lee D. Whetsel

IPC: G01R031/28

CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/318533 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594 ,  G11C29/006 ,  G11C29/022 ,  G11C29/48 ,  G11C2029/3202

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract translation: 测试晶片上的集成电路管芯的外围电路（350,360，ESD，BH），而不会物理接触管芯的接合焊盘。

公开(公告)号：US11848066B2

公开(公告)日：2023-12-19

申请号：US17714136

申请日：2022-04-05

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

IPC: G11C29/32 ,  G11C29/20 ,  G11C29/12 ,  H03K19/173 ,  H03K19/17728

CPC classification number: G11C29/32 ,  G11C29/1201 ,  G11C29/20 ,  H03K19/1737 ,  H03K19/17728 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/3202

Abstract: A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

公开(公告)号：US20230317192A1

公开(公告)日：2023-10-05

申请号：US17714136

申请日：2022-04-05

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

IPC: G11C29/32 ,  G11C29/20 ,  G11C29/12 ,  H03K19/17728 ,  H03K19/173

CPC classification number: G11C29/32 ,  G11C29/20 ,  G11C29/1201 ,  H03K19/17728 ,  H03K19/1737 ,  G11C2029/1204 ,  G11C2029/3202 ,  G11C2029/1202

Abstract: A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

公开(公告)号：US11749369B2

公开(公告)日：2023-09-05

申请号：US17943156

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Alberto Troia

IPC: G11C29/32 ,  G01R31/28 ,  G11C7/06 ,  G11C29/16 ,  G11C29/42

CPC classification number: G11C29/32 ,  G01R31/2815 ,  G11C7/06 ,  G11C29/16 ,  G11C29/42 ,  G11C2029/3202

Abstract: The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.

公开(公告)号：US20190004114A1

公开(公告)日：2019-01-03

申请号：US15636793

申请日：2017-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： JIAN SUN ,  CHAO MENG ,  XIAOXIAO LI ,  YINPENG LU

IPC: G01R31/3185 ,  G11C29/30 ,  G06F11/22 ,  H03K19/177 ,  H03K19/173

CPC classification number: G01R31/318536 ,  G01R31/318505 ,  G06F11/2205 ,  G11C29/12015 ,  G11C29/30 ,  G11C29/32 ,  G11C2029/3202 ,  H03K19/1735 ,  H03K19/1776

Abstract: A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.

公开(公告)号：US20180294042A1

公开(公告)日：2018-10-11

申请号：US15974033

申请日：2018-05-08

Applicant: International Business Machines Corporation

Inventor： Mitesh Agrawal ,  Benedikt Geukes ,  Krishnendu Mondal

IPC: G11C29/02 ,  G11C7/20 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C29/023 ,  G11C7/1012 ,  G11C7/20 ,  G11C7/22 ,  G11C29/12015 ,  G11C29/32 ,  G11C2029/0407 ,  G11C2029/3202

Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

公开(公告)号：US20180218778A1

公开(公告)日：2018-08-02

申请号：US15418543

申请日：2017-01-27

Applicant: QUALCOMM Incorporated

Inventor： Tapan Jyoti Chakraborty ,  Roberto Fabian Averbuj

IPC: G11C29/12 ,  G01R31/28

CPC classification number: G11C29/1201 ,  G01R31/2856 ,  G11C29/022 ,  G11C29/04 ,  G11C29/32 ,  G11C29/38 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/1208 ,  G11C2029/3202

Abstract: An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.

公开(公告)号：US20180217204A1

公开(公告)日：2018-08-02

申请号：US15420966

申请日：2017-01-31

Applicant: Mentor Graphics Corporation

Inventor： Yu Huang ,  Robert Randal Klingenberg ,  Huaxing Tang ,  Jayant Conrad D'Souza ,  Wu-Tung Cheng

IPC: G01R31/3177 ,  G11C29/38 ,  G11C29/44 ,  G01R31/317

CPC classification number: G11C29/44 ,  G11C29/20 ,  G11C29/24 ,  G11C29/38 ,  G11C29/40 ,  G11C2029/3202 ,  G11C2029/3602 ,  G11C2029/5604

Abstract: Various aspects of the present disclosed technology relate to techniques of locating defective memory cells based on scan chain diagnosis. Chain pattern responses of a circuit are first analyzed and at least one or more chain segment defect candidates on one faulty scan chain in the circuit and a fault model associated with the one faulty scan chain are determined. Here, each of the one or more chain segment defect candidates is a counter-based scan chain unit derived from a part or a whole of a memory array. Scan pattern responses are then analyzed to determine one or more memory cell defect candidates in the one or more chain segment defect candidates based on the information of the part or the whole of the memory array and the fault model.

公开(公告)号：US20180203067A1

公开(公告)日：2018-07-19

申请号：US15692048

申请日：2017-08-31

Applicant: MEDIATEK INC.

Inventor： Yiwei CHEN

IPC: G01R31/3185 ,  G11C29/32 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318536 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/31858 ,  G11C29/32 ,  G11C29/46 ,  G11C2029/3202

Abstract: A scan chain circuit is provided. The scan chain circuit includes first and second scan flip-flops and a clock generator. Each of the first and second scan flip-flops has a data-in terminal, a scan-in terminal, a clock terminal, and a data-out terminal. The clock terminals of the first and second scan flip-flop receive first and second clock signals respectively. The data-in terminal of the second scan flip-flop is coupled to the data-out terminal of the first scan flip-flop. During a scan shift cycle of the test mode, an enable pulse of a second clock-enable signal is delayed from an enable pulse of a first clock-enable signal, and the clock generator generates the first clock signal according to the scan clock signal and the first clock-enable signal and further generates the second clock signal according to the scan clock signal and the second clock-enable signal.