公开(公告)号：US5710710A

公开(公告)日：1998-01-20

申请号：US561692

申请日：1995-11-22

申请人： William P. Owen ,  Judd Sheets

发明人： William P. Owen ,  Judd Sheets

IPC分类号： G01R23/02 ,  G01R23/10 ,  G01R23/00 ,  G06F17/00

CPC分类号： G01R23/10 ,  G01R23/02

摘要： An improved frequency counter for more reliably reading the frequency of low level signals by employing a method of separating the desired signal from undesirable noise related signals, wherein the frequency counter comprises signal input amplifier circuitry, a frequency modulator circuit for phase shifting the self-oscillation frequency of the undesired signal to isolate it from the valid signal, a prescaler circuit, a frequency or pulse counter driven by the output of the prescaler, and a correlator circuit for differentiating the self-oscillation frequencies from the main signal frequency so as to reduce false correlations between the self-oscillation, or noise, and valid signals.

摘要翻译： 一种改进的频率计数器，用于通过采用将期望信号与不期望的噪声相关信号分离的方法更可靠地读取低电平信号的频率，其中频率计数器包括信号输入放大器电路，用于相位自振荡的频率调制器电路 不需要的信号的频率使其与有效信号隔离，预分频器电路，由预分频器的输出驱动的频率或脉冲计数器，以及用于将自振荡频率与主信号频率区分开来的相关器电路，以便减少 自振荡或噪声与有效信号之间的假相关。

公开(公告)号：US5487097A

公开(公告)日：1996-01-23

申请号：US291285

申请日：1994-08-16

申请人： Makoto Hatakenaka ,  Haruo Sakurai ,  Hideo Nagano

发明人： Makoto Hatakenaka ,  Haruo Sakurai ,  Hideo Nagano

IPC分类号： G01R23/00 ,  G01R23/10 ,  H03K21/00

CPC分类号： G01R23/005 ,  G01R23/10

摘要： It is an object to accurately obtain the period of the horizontal synchronizing signal in the video signal. The number of internal pulses are measured in a predetermined measurement period defined by the horizontal synchronizing signal. It is assumed that the periods of the horizontal synchronizing signal and the internal pulse are denoted as T.sub.H and T.sub.S, and the measurement period is defined by one period of a divided signal NS which is obtained by N-dividing the horizontal synchronizing signal. In this case, the length of the measurement period is N.multidot.T.sub.H. The period of the horizontal synchronizing signal is obtained when the internal pulse is activated K times in the measurement period. After the measurement period is started, the divided signal NS transits between the Kth activation of the internal pulse and the (K+1)th activation, and the measurement period is ended. Accordingly, there is the relation of T.sub.S .multidot.K

摘要翻译： 其目的在于准确地获得视频信号中的水平同步信号的周期。 在由水平同步信号定义的预定测量周期内测量内部脉冲的数量。 假设水平同步信号和内部脉冲的周期被表示为TH和TS，并且测量周期由通过N分割水平同步信号获得的分频信号NS的一个周期来定义。 在这种情况下，测量周期的长度为N×TH。 在测量周期内内部脉冲激活K次时，获得水平同步信号的周期。 在测量周期开始之后，分频信号NS在内部脉冲的第K次激活和第（K + 1）激活之间转换，并且测量周期结束。 因此，存在TSxK

公开(公告)号：US5097490A

公开(公告)日：1992-03-17

申请号：US640985

申请日：1991-01-14

申请人： Rand H. Hulsing, II ,  Charles K. Lee

发明人： Rand H. Hulsing, II ,  Charles K. Lee

IPC分类号： G01R23/10

CPC分类号： G01R23/10

摘要： Apparatus and method for counting frequency of a signal with improved resolution. Frequency counters (10, 60, and 100) accumulate clock cycles from a reference oscillator (20) during a sample interval. In the simplest form of the frequency counter, the reference clock signal is inverted and both the noninverted and inverted clock cycles are accumulated in separate counters (40 and 44). The accumulated counts are totaled in a summing circuit (48) and divided by two to determine their average, thereby doubling the resolution of the frequency counter. A more complex embodiment of the invention corrects a raw count of cycles of an input signal (12) that are accumulated during an extended sample interval defined by successive rising edges of a sample signal (114). The fractional portion of a cycle of the input waveform that occurred prior to the beginning of the extended sample interval is added to the raw count and the fractional portion of the input waveform that occurred after the end of the extended sample interval is subtracted. These fractional portions are defined as ratios of a partial count of clock cycles to a full count of clock cycled. The partial count is the number of clock cycles occurring between a rising edge of the sample signal and the next rising edge of the input signal, while the full count is the number of clock cycles occurring between successive rising edges of the input signal. One-half clock logic circuits (126 and 136) double the resolution of the counts accumulated by a partial counter (122) and a full counter (142), thereby doubling the resolution with which the ratios of the two counts are determined.

摘要翻译： 用改进分辨率对信号频率进行计数的装置和方法。 频率计数器（10,60和100）在采样间隔期间从参考振荡器（20）累加时钟周期。 在频率计数器的最简单形式中，参考时钟信号被反相，同相和反相时钟周期都被累积在单独的计数器（40和44）中。 积累的计数总计在求和电路（48）中，并被除以2以确定它们的平均值，从而使频率计数器的分辨率加倍。 本发明的更复杂的实施例校正在由采样信号（114）的连续上升沿限定的扩展采样间隔期间累积的输入信号（12）的周期的原始计数。 在扩展采样间隔开始之前发生的输入波形的周期的小数部分被加到原始计数，并且减去在扩展采样间隔结束之后发生的输入波形的小数部分。 这些小数部分定义为时钟周期的部分计数与循环时钟的完整计数的比率。 部分计数是在采样信号的上升沿和输入信号的下一个上升沿之间发生的时钟周期数，而全部计数是在输入信号的连续上升沿之间发生的时钟周期数。 二分之一时钟逻辑电路（126和136）使由部分计数器（122）和全计数器（142）累积的计数的分辨率翻一倍，从而将确定两个计数的比率的分辨率加倍。

公开(公告)号：US5090034A

公开(公告)日：1992-02-18

申请号：US587747

申请日：1990-09-25

申请人： K. Peter Ganza

发明人： K. Peter Ganza

IPC分类号： G01R23/10

CPC分类号： G01R23/10

摘要： An event counter has dual counting channels, each employing a ripple counter, and a timing generator supplying square wave switching signals of opposite phases to gates at the inputs of the two counters, the switching signals having a much greater periodicity than that of events to be counted, so that one, and only one, of the counters is counting at any one time. The timing generator also generates control signals to transfer a count from whichever counter is inactive to an associated latch and then reset the counter. When a counter is again enabled, the switching signal is also used to enable output from the latch of the previously stored count. This arrangement enables ripple counters to be used in an arrangement providing both continuous counting and continuous output availability.

摘要翻译： 事件计数器具有双计数通道，每个采用纹波计数器，以及定时发生器，在两个计数器的输入端向门提供相反相位的方波切换信号，开关信号的周期大于 计数，所以一个，只有一个柜台在任何时候都在计数。 定时发生器还产生控制信号，以将来自无效计数器的计数转移到相关联的锁存器，然后重置计数器。 当再次使能计数器时，切换信号也用于使锁存器输出先前存储的计数。 这种布置使得波纹计数器能够在提供连续计数和连续输出可用性的布置中使用。

公开(公告)号：US4837705A

公开(公告)日：1989-06-06

申请号：US18899

申请日：1987-02-25

申请人： James M. Mussler ,  Jane P. Arnold

发明人： James M. Mussler ,  Jane P. Arnold

IPC分类号： G01R23/10 ,  G01R23/15

CPC分类号： G01R23/15 ,  G01R23/10

摘要： A method of determining the rate of change of frequency of a plurality of randomly occurring events begins by counting the number of random events which occur within a plurality of predetermined sampling intervals to obtain a plurality of count values, each corresponding to one of the sampling intervals. These count values are stored in a memory table and the count values which correspond to the most recent set of N of the sampling intervals is summed to obtain a first accumulated count. A second accumulated count is obtained by summing the count values which correspond to a second set of N of the sampling intervals, preceding the most recent set. The rate of change of event frequency is then calculated by dividing the logarithm of (S.sub.1 /S.sub.2) by the number N. The value of the number N is dynamically adjusted for subsequent calculations based on the incoming frequency of random events.

摘要翻译： 确定多个随机发生事件的频率变化率的方法开始于在多个预定采样间隔内发生的随机事件的数量，以获得多个计数值，每个计数值对应于采样间隔 。 这些计数值被存储在存储器表中，并且对应于最近采样间隔的N个集合的计数值被相加以获得第一累积计数。 通过将对应于最近设置的采样间隔的第二组N的计数值相加来获得第二累加计数。 然后通过将（S1 / S2）的对数除以数字N来计算事件频率的变化率。根据随机事件的输入频率对数N的值进行动态调整，用于后续计算。

公开(公告)号：US4788646A

公开(公告)日：1988-11-29

申请号：US810760

申请日：1985-12-19

申请人： Peter J. Herzl

发明人： Peter J. Herzl

IPC分类号： G01R23/02 ,  G01R23/10

CPC分类号： G01R23/10 ,  G01R23/02

摘要： A converter for converting a variable data frequency which lies in a low frequency range whose upper limit is about 200 Hz to a corresponding digital value. The converter includes an electronic counter having an enabling input and a count input. Derived from the data frequency is a data signal whose frequency is a given sub-multiple of the data frequency as selected by a digital computer. The data signal is applied to the enabling input to enable the counter for a period equal to the duration of a half cycle of the incoming data signal. Derived from an electronic clock operating at a constant frequency above 10,000 Hz is a clock signal whose pulse repetition rate is a given sub-multiple thereof as selected by the computer. These clock pulses are applied to the count input of the counter whereby the count accumulated therein is determined by the duration of the enabling period. This count is entered in the computer which, having selected the data signal and the clock signal, knows the scale factor, and can then, on the basis of the entered count, calculate the true period (P) of the data frequency (F) and provide a digital output corresponding to the frequency as determined by the equation F=1/P.

摘要翻译： A转换器，用于将位于上限为约200Hz的低频范围的可变数据频率转换为相应的数字值。 转换器包括具有使能输入和计数输入的电子计数器。 从数据频率得出的数据信号的频率是由数字计算机选择的数据频率的给定子倍数。 数据信号被施加到使能输入以使计数器能够等于输入数据信号的半周期的持续时间。 来自以10,000Hz以上恒定频率工作的电子时钟是由计算机选择的脉冲重复率是其给定子倍数的时钟信号。 这些时钟脉冲被施加到计数器的计数输入，由此累加其中的计数由使能周期的持续时间确定。 该计数输入到已经选择了数据信号和时钟信号的计算机中知道比例因子，然后可以根据输入的计数来计算数据频率（F）的真实周期（P） 并提供对应于由等式F = 1 / P确定的频率的数字输出。

公开(公告)号：US4733169A

公开(公告)日：1988-03-22

申请号：US852155

申请日：1986-04-15

申请人： Mervin L. Grindahl

发明人： Mervin L. Grindahl

IPC分类号： G01R23/10

CPC分类号： G01R23/10

摘要： A frequency detector completely implemented with digital logic circuitry is disclosed. The frequency detector hereof employs a unique phase locked loop digitally implemented with asynchronous ripple counters, and a digitally implemented amplitude comparator and signal integrator. The detector is especially adapted for implementation in CMOS hardware, or similar hardware having low current drain characteristics. The selectivity of the detector can be set to a narrow bandwidth for excellent noise discrimination characteristics.

摘要翻译： 公开了一种完全用数字逻辑电路实现的频率检测器。 其频率检测器采用数字实现的异步纹波计数器和数字实现的幅度比较器和信号积分器的独特的锁相环。 该检测器特别适用于CMOS硬件或具有低电流消耗特性的类似硬件。 可以将检测器的选择性设置为窄带宽以获得优异的噪声鉴别特性。

公开(公告)号：US4414504A

公开(公告)日：1983-11-08

申请号：US204097

申请日：1980-11-05

申请人： Howard L. Kennedy

发明人： Howard L. Kennedy

IPC分类号： G01S13/50 ,  G01R23/10 ,  G01S11/10 ,  G01R23/02

CPC分类号： G01R23/10 ,  G01S11/10

摘要： A system for measuring Doppler frequency cycle count over a predetermined time period wherein a phase locked VCO is operated at N times the Doppler to allow measurement of both integral and fractional cycles. The resolution of the measurement is a function of the factor N.

摘要翻译： 一种用于在预定时间段内测量多普勒频率周期计数的系统，其中锁相VCO在多普勒的N倍下操作，以允许测量积分和分数周期。 测量的分辨率是因子N的函数。

公开(公告)号：US4224574A

公开(公告)日：1980-09-23

申请号：US946474

申请日：1978-09-28

申请人： Mark L. Shaw

发明人： Mark L. Shaw

IPC分类号： G01R23/10 ,  G06F7/68 ,  H03K5/00 ,  H04B1/00 ,  H04B7/00

CPC分类号： G01R23/10 ,  G06F7/68 ,  H03K5/00

摘要： A digital frequency quadrupler which provides output pulses at a rate equal to four times the number of input pulses. The input frequency range is extended by logic which allows additional pulses to be inserted in the output as the input frequency increases causing overlap between adjacent pulses. When the maximum upper range limit is reached the quadrupler saturates, that is, the output frequency becomes constant.

摘要翻译： 数字频率倍频器，以等于输入脉冲数量的四倍的速率提供输出脉冲。 输入频率范围通过逻辑延长，允许在输入频率增加时附加脉冲被插入，从而导致相邻脉冲之间的重叠。 当达到最大上限极限时，四倍子饱和，即输出频率变为恒定。

公开(公告)号：US4165459A

公开(公告)日：1979-08-21

申请号：US869643

申请日：1978-01-16

申请人： Walter R. Curtice

发明人： Walter R. Curtice

IPC分类号： G01R23/00 ,  G01R23/10 ,  G04F10/00 ,  G01R23/02 ,  H03K21/30

CPC分类号： G01R23/005 ,  G01R23/10 ,  G04F10/00

摘要： The interval between arrival of two time displaced signals is measured with a resolution less than 0.5 nanoseconds by electronic vernier techniques utilizing transferred electron logic device circuits. The first arriving signal triggers a first clock generator of pulse period T.sub.C, the pulses from which are counted by a first counter and a second counter. The second arriving signal triggers a second clock pulse generator having a pulse period T.sub.V, the first pulse therefrom disabling the first counter at a count of M. As T.sub.V

摘要翻译： 两个时间位移信号到达之间的间隔通过利用传输的电子逻辑器件电路的电子游标技术以小于0.5纳秒的分辨率来测量。 第一到达信号触发脉冲周期TC的第一时钟发生器，其脉冲由第一计数器和第二计数器计数。 第二到达信号触发具有脉冲周期TV的第二时钟脉冲发生器，其中的第一脉冲从而以M的计数禁用第一计数器。由于来自两个时钟脉冲发生器的脉冲的TC与TC的重合将最终导致禁用 时间间隔DELTA T由下式计算：DELTA T =（N-1）TC-（NM）TV。