公开(公告)号：US06171899B2

公开(公告)日：2001-01-09

申请号：US09267535

申请日：1999-03-12

申请人： Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

发明人： Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/76838

摘要： A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer. A photolithography and etching process is performed to remove a part of the second conductive layer. The second metal layer remaining on the inter-layer dielectric layer is used as a wiring line for interconnection. The glue layer remaining on the dielectric film is used as an upper electrode.

摘要翻译： 一种制造电容器的方法。 在所提供的基板上形成第一金属层。 在第一金属层上形成电介质膜。 电介质膜可以是单层结构或包括各种介电材料的多层结构。 进行快速热处理（RTP），例如快速热退火或等离子体处理，以提高电介质膜的质量。 进行光刻和蚀刻处理以去除电介质膜和第一金属层的一部分以暴露层间电介质层的一部分。 剩余的第一导电层用作下电极。 在暴露的层间电介质层和电介质膜上进行常规的互连工艺。 例如，在暴露的层间电介质层和电介质膜上形成胶层。 第二金属层形成在胶层上。 执行光刻和蚀刻工艺以去除第二导电层的一部分。 残留在层间电介质层上的第二金属层用作互连布线。 残留在电介质膜上的胶层用作上电极。

公开(公告)号：US6025241A

公开(公告)日：2000-02-15

申请号：US73576

申请日：1998-05-06

申请人： Tony Lin ,  Water Lur

发明人： Tony Lin ,  Water Lur

IPC分类号： H01L21/3115 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/66507 ,  H01L29/6659 ,  H01L21/31155 ,  Y10S148/147

摘要： A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer. Through this method, the resultant semiconductor device is reliable in operation since the drawback of the occurrence of leakage current or short-circuit that could be otherwise resulted between the self-aligned silicide and the substrate owing to the short-channel effect can be eliminated. Moreover, the resultant semiconductor device has increased anti-static capability that can protect the semiconductor device against electro-static damage.

摘要翻译： 提供了一种用于制造具有自对准硅化物的半导体器件（例如MOS（金属氧化物半导体）晶体管）的方法。 该方法可以防止硅化物与衬底之间的结漏电，从而使所得的半导体器件具有可靠的性能。 该方法包括制备半导体衬底的步骤; 在所述衬底上形成至少一个晶体管元件，所述晶体管元件包括一对源极/漏极区域，栅极，所述栅极上的电介质层以及所述栅极侧壁上的间隔物; 并且进行离子轰击处理，以将邻近间隔物顶部的电介质层的一部分输送到间隔物的底部旁边。 通过该方法，由于短沟道效应，可以消除由于短路导致的自对准硅化物和衬底之间的漏电流或短路的缺点，所以得到的半导体器件工作可靠。 此外，所得到的半导体器件具有增强的抗静电能力，可以保护半导体器件免受静电损坏。

公开(公告)号：US5739046A

公开(公告)日：1998-04-14

申请号：US657058

申请日：1996-05-28

申请人： Water Lur ,  Shih-Chanh Chang ,  Jiun Yuan Wu ,  Der Yuan Wu

发明人： Water Lur ,  Shih-Chanh Chang ,  Jiun Yuan Wu ,  Der Yuan Wu

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76864 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856

摘要： A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds. The final step is to release the system stress by tempering the layer at a temperature of between about 600.degree. to 750.degree. C. This completes the barrier layer which has good adhesion to the dielectric layer(s) and, therefore, promotes improved pad bonding yield.

摘要翻译： 描述形成金属扩散阻挡层的新方法。 在半导体衬底中形成半导体器件结构。 至少一个电介质层覆盖半导体结构，并且至少一个接触孔已经通过介电层被打开到半导体衬底。 现在通过以下步骤形成金属扩散阻挡层：在第一步骤中，将薄的钛层保形地沉积在电介质层的表面和接触开口内，并在氮气气氛中退火 在约580℃至630℃之间的温度下进行约20至120秒。 第二步是在金属前介电层上形成稳定且粘合的钛化合物，并在接触硅上形成低电阻硅化物，在约800-900℃之间退火约5至60秒 。 最后一步是通过在约600至750℃的温度下回火层来释放系统应力。这完成了与电介质层具有良好粘附性的阻挡层，因此促进改进的焊盘接合 产量。

公开(公告)号：US5668394A

公开(公告)日：1997-09-16

申请号：US582599

申请日：1996-01-03

申请人： Water Lur ,  Cheng-Han Huang

发明人： Water Lur ,  Cheng-Han Huang

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/76

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  Y10S257/915

摘要： A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited overlying the gate polysilicon layer. A of tungsten silicide is deposited overlying the thin diffusion barrier layer wherein a reaction gas in the deposition contains fluorine atoms and wherein fluorine atoms are incorporated into the tungsten layer. The gate polysilicon, thin conducting barrier, and tungsten silicide layers are patterned form the polycide gate structures. The wafer is annealed complete formation of the polycide gate structures wherein number of fluorine atoms from the tungsten silicide layer into the gate polysilicon layer are minimized by presence of the thin conducting diffusion barrier layer wherein because the diffusion of the fluorine atoms is the thickness of the gate oxide layer does not This prevents the device from degradation such as voltage shift and saturation current descrease.

摘要翻译： 描述了一种制造多晶硅栅极的新方法。 栅极多晶硅层在衬底的表面上提供栅极氧化物层。 沉积在栅极多晶硅层上的薄导电扩散势垒。 沉积硅化硅的A，覆盖薄扩散阻挡层，其中沉积中的反应气体含有氟原子，并且其中氟原子被结合到钨层中。 门多晶硅，薄导电屏障和硅化钨层由多晶硅栅极结构构图。 晶片经过退火完成形成多晶硅栅极结构，其中从硅化钨层到栅极多晶硅层的氟原子数量通过存在薄导电扩散阻挡层而最小化，其中由于氟原子的扩散是 栅极氧化层不会阻止器件劣化，如电压偏移和饱和电流下降。

公开(公告)号：US5633198A

公开(公告)日：1997-05-27

申请号：US536859

申请日：1995-09-29

申请人： Water Lur ,  Jiun Y. Wu

发明人： Water Lur ,  Jiun Y. Wu

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S148/161 ,  Y10S438/927 ,  Y10S438/978

摘要： A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.

摘要翻译： 实现了使用金属接触形状，接触/通孔轮廓和金属线的新设计的金属化的新方法，其具有显着降低的电流密度和改善金属线的电迁移。 金属触点形成为矩形形状而不是具有与电流方向垂直的较宽侧的正方形形状。 接触开口被制成具有凹形轮廓，其可以提供比具有接触底部附近的垂直轮廓的常规开口更宽的导电横截面面积。 在宽且高电流的金属线中形成间隙，通过均匀地利用整个金属线，可以有效地降低电流密度。

公开(公告)号：US5633197A

公开(公告)日：1997-05-27

申请号：US536858

申请日：1995-09-29

申请人： Water Lur ,  Jiun Y. Wu

发明人： Water Lur ,  Jiun Y. Wu

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S148/161 ,  Y10S438/927 ,  Y10S438/978

摘要： A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.

摘要翻译： 实现了使用金属接触形状，接触/通孔轮廓和金属线的新设计的金属化的新方法，其具有显着降低的电流密度和改善金属线的电迁移。 金属触点形成为矩形形状而不是具有与电流方向垂直的较宽侧的正方形形状。 接触开口被制成具有凹形轮廓，其可以提供比具有接触底部附近的垂直轮廓的常规开口更宽的导电横截面面积。 在宽且高电流的金属线中形成间隙，通过均匀地利用整个金属线，可以有效地降低电流密度。

公开(公告)号：US5599746A

公开(公告)日：1997-02-04

申请号：US239229

申请日：1994-05-06

申请人： Water Lur ,  Der-Yuan Wu

发明人： Water Lur ,  Der-Yuan Wu

IPC分类号： H01L21/301 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76889 ,  Y10S438/964

摘要： A method for eliminating the peeling of polycide at the edge of a wafer used to fabricate semi-conductors and integrated circuits. A global rough surface is formed on the wafer. The rough surface on the substrate wafer releases most of the thermal stress between the silicide and polysilicon layers which are found in conventional devices. A "peel free" surface results and the particle problem is lessened.

摘要翻译： 一种用于消除在用于制造半导体和集成电路的晶片的边缘处的多晶硅化合物的剥离的方法。 在晶片上形成全局粗糙表面。 衬底晶圆上的粗糙表面释放了常规器件中发现的硅化物和多晶硅层之间的大部分热应力。 “剥离”表面结果，粒子问题减弱。

公开(公告)号：US5517062A

公开(公告)日：1996-05-14

申请号：US387432

申请日：1995-02-13

申请人： Water Lur ,  J. Y. Wu

发明人： Water Lur ,  J. Y. Wu

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L29/06

CPC分类号： H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02299 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/7682 ,  H01L2221/1047

摘要： A new method of forming stress releasing voids within the intermetal dielectric of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. A silicon oxide layer is deposited overlying the first patterned metal layer. A silicon nitride layer is deposited over the silicon oxide layer. A metal layer is deposited over the silicon nitride layer and etched to form silicon nodules on the surface of the silicon nitride layer. The silicon nitride layer is etched away to the underlying silicon oxide layer wherein the silicon nitride under the silicon nodules remains in the form of pillars. The surface of the silicon oxide layer is coated with a spin-on-glass material which is baked and cured. The silicon nodules and silicon nitride pillars are removed, leaving voids within the spin-on-glass layer. A second layer of silicon oxide is deposited overlying the spin-on-glass layer to complete formation of the porous intermetal dielectric of the said integrated circuit.

摘要翻译： 实现了在集成电路的金属间电介质内形成应力释放空隙的新方法。 在半导体衬底上和半导体衬底上的半导体器件结构上提供第一层图案化金属化层。 沉积第一图案化金属层上的氧化硅层。 在氧化硅层上沉积氮化硅层。 金属层沉积在氮化硅层上并被蚀刻以在氮化硅层的表面上形成硅结节。 将氮化硅层蚀刻掉到下面的氧化硅层上，其中硅结晶下面的氮化硅保持为柱状。 氧化硅层的表面涂覆有烘烤和固化的旋涂玻璃材料。 硅结节和氮化硅柱被去除，在旋涂玻璃层内留下空隙。 第二层氧化硅沉积在旋涂玻璃层上，以完成所述集成电路的多孔金属间电介质的形成。

公开(公告)号：US5492848A

公开(公告)日：1996-02-20

申请号：US214593

申请日：1994-03-18

申请人： Water Lur ,  Jiunn-Yuan Wu ,  Cheng-Hen Huang

发明人： Water Lur ,  Jiunn-Yuan Wu ,  Cheng-Hen Huang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/92 ,  Y10S438/947

摘要： A technique for making a MOST capacitor for use in a DRAM cell utilizes silicon nodules after metal etching. The silicon nodules are used as a mask to selectively form deep grooves in a polysilicon electrode of the capacitor.

摘要翻译： 用于制造用于DRAM单元的MOST电容器的技术在金属蚀刻之后利用硅结节。 硅结节用作掩模以在电容器的多晶硅电极中选择性地形成深槽。

公开(公告)号：US5482882A

公开(公告)日：1996-01-09

申请号：US214592

申请日：1994-03-18

申请人： Water Lur ,  Pin-Iuh Chen ,  Jiunn-Yuan Wu

发明人： Water Lur ,  Pin-Iuh Chen ,  Jiunn-Yuan Wu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/00 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/92 ,  Y10S438/947

摘要： A MOST capacitor for use in a DRAM cell by using non-uniform silicide formations on polysilicon to define a plurality of polysilicon pillars. Unreacted polysilicon islands are used as a mask to selectively form the pillars in the polysilicon electrode layer.

摘要翻译： 一种用于DRAM单元的MOST电容器，其通过在多晶硅上使用不均匀的硅化物结构来限定多个多晶硅柱。 未反应的多晶硅岛用作掩模以在多晶硅电极层中选择性地形成柱。