公开(公告)号：US20230031861A1

公开(公告)日：2023-02-02

申请号：US17967200

申请日：2022-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/36

Abstract: A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

公开(公告)号：US20220415825A1

公开(公告)日：2022-12-29

申请号：US17549026

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Junghoo SHIN ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having sp3 bonds to carbons having sp2 bonds in the graphene material is 1 or less.

公开(公告)号：US20220415800A1

公开(公告)日：2022-12-29

申请号：US17893349

申请日：2022-08-23

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE ,  Kyung-Eun BYUN ,  Hyeonsuk SHIN ,  Seokmo HONG

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/108

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

公开(公告)号：US20220171098A1

公开(公告)日：2022-06-02

申请号：US17459537

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin CHOI ,  Hyeonjin SHIN ,  Changseok LEE ,  Sangwon KIM

IPC: G02B1/113 ,  H01L27/146 ,  H01L21/027 ,  H01L31/0216 ,  H01L31/052 ,  H01L51/52 ,  G03F7/09

Abstract: Provided are an amorphous boron nitride film and an anti-reflection coating structure including the amorphous boron nitride film. The amorphous boron nitride film has an amorphous structure including an sp3 hybrid bond and an sp2 hybrid bond, in which a ratio of the sp3 hybrid bond in the amorphous boron nitride film is less than about 20%.

公开(公告)号：US20210234015A1

公开(公告)日：2021-07-29

申请号：US17060696

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun LEE ,  Minsu SEOL ,  Ho Won JANG ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04 ,  H01L29/66

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

公开(公告)号：US20210163296A1

公开(公告)日：2021-06-03

申请号：US17060893

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Changhyun KIM ,  Changseok LEE ,  Yeonchoo CHO

IPC: C01B32/186

Abstract: A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

公开(公告)号：US20210151678A1

公开(公告)日：2021-05-20

申请号：US17094121

申请日：2020-11-10

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun LEE ,  Houk JANG ,  Donhee HAM ,  Chengye LIU ,  Henry HINTON ,  Haeryong KIM ,  Hyeonjin SHIN

IPC: H01L45/00 ,  H01L27/24

Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

公开(公告)号：US20210125930A1

公开(公告)日：2021-04-29

申请号：US17082530

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE ,  Kyung-Eun BYUN ,  Hyeonsuk SHIN ,  Seokmo HONG

IPC: H01L23/532 ,  H01L27/108 ,  H01L23/522

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

公开(公告)号：US20210123161A1

公开(公告)日：2021-04-29

申请号：US17082502

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Seokmo HONG ,  Minhyun LEE ,  Seunggeol NAM ,  Kyungyeol MA

IPC: C30B29/38 ,  H01L21/02

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US20210074815A1

公开(公告)日：2021-03-11

申请号：US17087968

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Seunggeol NAM ,  Seongjun PARK ,  Yunseong LEE

IPC: H01L29/16 ,  H01L21/02 ,  C01B32/186

Abstract: Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.