公开(公告)号：US20140063933A1

公开(公告)日：2014-03-06

申请号：US14076427

申请日：2013-11-11

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Hari M. Rao ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1693

Abstract: A first write driver applies a first voltage above a fixed potential to a first terminal. A second write driver applies a second voltage that is higher above the fixed potential than the first voltage to a second terminal. There is at least one magnetic tunnel junction (MTJ) structure coupled at the first terminal at a first side to the first write driver and coupled at the second terminal at a second side to the second write driver. The first side of the MTJ structure receives the first voltage and the second side of the MTJ structure receives a ground voltage to change from a first state to a second state. The second side of the MTJ structure receives the second voltage and the first side of the MTJ structure receives the ground voltage to change from the second state to the first state.

Abstract translation: 第一写入驱动器将高于固定电位的第一电压施加到第一端子。 第二写入驱动器将比固定电位高于第一电压的第二电压施加到第二端子。 至少有一个磁隧道结（MTJ）结构在第一端处的第一端耦合到第一写入驱动器，并且在第二端处的第二端耦合到第二写入驱动器。 MTJ结构的第一侧接收第一电压，并且MTJ结构的第二侧接收地电压以从第一状态变为第二状态。 MTJ结构的第二面接收第二电压，并且MTJ结构的第一侧接收地电压以从第二状态变为第一状态。

公开(公告)号：US20140043924A1

公开(公告)日：2014-02-13

申请号：US14056990

申请日：2013-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L43/12

CPC classification number: G11C11/1677 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/161 ,  G11C29/18 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/2602 ,  H01L43/12

Abstract: Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

Abstract translation: 所公开的实施例包括具有多个位线和多个排列成列的源极线的存储器阵列。 多行字线被排列成行。 多个存储元件具有与存储器阵列电分离的存储元件的第一子集和耦合到存储器阵列的存储元件的第二子集。 存储器阵列还包括多个位单元，每个位单元包括来自耦合到至少两个晶体管的存储元件的第二子集的一个存储元件。 位单元耦合到多个位线和多个源极线。 每个晶体管耦合到一个字线。 存储器阵列还可以包括选择高性能模式和高密度模式的逻辑。

公开(公告)号：US20140015080A1

公开(公告)日：2014-01-16

申请号：US14036409

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Seung H. Kang ,  Xia Li ,  Shiqun Gu ,  Kangho Lee ,  Xiaochun Zhu

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.

Abstract translation: 用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）装置包括与至少一个控制装置通信的第一导电互连和通过形成在电介质钝化屏障中的通孔连接到第一导电互连的第一电极，其使用 第一个面具。 该装置具有用于存储耦合到第一电极的数据的MTJ堆叠。 MTJ堆叠的一部分具有基于第二掩模的横向尺寸。 由第二掩模限定的部分在接触通孔之上。 第二电极耦合到MTJ堆叠并且还具有由第二掩模限定的横向尺寸。 第一电极和MTJ堆叠的一部分由第三掩模限定。 第二导电互连件耦合到第二电极和至少一个其它控制装置。

公开(公告)号：US20130320468A1

公开(公告)日：2013-12-05

申请号：US13959710

申请日：2013-08-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/10 ,  H01L43/12

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/12

Abstract: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

Abstract translation: 根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。