公开(公告)号：US11748298B2

公开(公告)日：2023-09-05

申请号：US17826674

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048

CPC classification number: G06F15/8007 ,  G06F9/3004 ,  G06F13/00 ,  G06F13/4027 ,  G06N3/044 ,  G06N3/045 ,  G06N3/048 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US11663449B2

公开(公告)日：2023-05-30

申请号：US16648169

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Arnab Paul ,  Narayan Srinivasa

IPC: G06F16/00 ,  G06N3/049 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/08

Abstract: Techniques and mechanisms for providing a logical state machine with a spiking neural network which includes multiple sets of nodes. Each of the multiple sets of nodes is to implement a different respective state, and each of the multiple spike trains is provided to respective nodes of each of the multiple sets of nodes. A given state of the logical state machine is implemented by configuring respective activation modes of each node of the corresponding set of nodes. The activation mode of a given node enables that node to signal, responsive to its corresponding spike train, that a respective state transition of the logical state machine is to be performed. In another embodiment, the multiple spike trains each represent a different respective character in a system used by data evaluated with the spiking neural network.

公开(公告)号：US11631198B2

公开(公告)日：2023-04-18

申请号：US17355271

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Abhishek Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Farshad Akhbari

IPC: G06T9/00 ,  G06T1/60 ,  G06N3/063 ,  G06N3/04 ,  G06N3/084 ,  G06F12/02 ,  G06T1/20

Abstract: An apparatus to facilitate compute compression is disclosed. The apparatus includes a graphics processing unit including mapping logic to map a first block of integer pixel data to a compression block and compression logic to compress the compression block.

公开(公告)号：US11609856B2

公开(公告)日：2023-03-21

申请号：US17206514

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/08 ,  G06F12/0837 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06F12/0815 ,  G06N3/063 ,  G06N3/04 ,  G06N3/084 ,  G06N3/088

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US11592817B2

公开(公告)日：2023-02-28

申请号：US15581124

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G05D1/00 ,  G06F9/50 ,  G06N3/084

Abstract: A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.

公开(公告)号：US11544564B2

公开(公告)日：2023-01-03

申请号：US16957056

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Arnab Paul ,  Narayan Srinivasa

IPC: G06N3/08 ,  G06N3/04

Abstract: Techniques and mechanisms for performing a Bayesian inference with a spiking neural network. In an embodiment, a parent node of the spiking neural network receives a first bias signal which is periodic. The parent node communicates a likelihood signal to a child node, wherein the parent node and the child node correspond to a first condition and a second condition, respectively. Based on a phase change which is applied to the first bias signal, the likelihood signal indicates a probability of the first condition. The child node also receives a signal which indicates an instance of the second condition. Based on the indication and a second bias signal, the child node signals to the first node that an adjustment is to be made to the phase change applied to the first bias signal. After the adjustment, the likelihood signal indicates an updated probability of the first condition.

公开(公告)号：US11360933B2

公开(公告)日：2022-06-14

申请号：US16744407

申请日：2020-01-16

Applicant: Intel Corporation

Inventor： Altug Koker ,  Farshad Akhbari ,  Feng Chen ,  Dukhwan Kim ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu

IPC: G06F15/80 ,  G06F13/40 ,  G06T1/20 ,  G06F9/30 ,  G06F13/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

公开(公告)号：US11222392B2

公开(公告)日：2022-01-11

申请号：US16531763

申请日：2019-08-05

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US20210294649A1

公开(公告)日：2021-09-23

申请号：US17206514

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Prasoonkumar Surti ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Abhishek R. Appu ,  Nicolas C. Galoppo Von Borries ,  Joydeep Ray ,  Narayan Srinivasa ,  Feng Chen ,  Ben J. Ashbaugh ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Altug Koker

IPC: G06F9/48 ,  G06N3/04 ,  G06F12/12

Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210264163A1

公开(公告)日：2021-08-26

申请号：US17173732

申请日：2021-02-11

Applicant: Intel Corporation

Inventor： Mayuresh M. Varerkar ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Sherine Abdelhak ,  Sachin Godse ,  Farshad Akhbari ,  Narayan Srinivasa ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Dukhwan Kim ,  Feng Chen ,  Abhishek R. Appu ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06K9/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.