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81.发明授权Array substrate, liquid crystal panel, liquid crystal display and driving method thereof 有权阵列基板，液晶面板，液晶显示器及其驱动方法公开(公告)号：US08767158B2
公开(公告)日：2014-07-01
申请号：US14048572
申请日：2013-10-08
Inventor： Zheng Wang , Xibin Shao
IPC: G02F1/1343
CPC classification number: G02F1/133509 , G02F1/134309 , G02F1/134363 , G02F2001/134318 , G02F2001/134372 , G09G3/3614 , G09G3/3648
Abstract: A liquid crystal panel having an array substrate, a color filter substrate, a plurality of pixel units provided on both of the array substrate and the color filter substrate, a common electrode and a pixel electrode being provided in each of the pixel units such that when polarity of voltage difference between the pixel electrode and the common electrode in one first pixel unit is identical to that in one second pixel unit, the direction of an electric field formed between the pixel electrode and the common electrode and for driving liquid crystal molecules to display at a gray level in the first pixel unit is opposite to that in the second pixel unit.
Abstract translation: 具有阵列基板的液晶面板，滤色器基板，设置在阵列基板和滤色器基板两者上的多个像素单元，在每个像素单元中设置公共电极和像素电极， 一个第一像素单元中的像素电极和公共电极之间的电压差的极性与一个第二像素单元中的电压差的极性相同，在像素电极和公共电极之间形成的电场的方向和用于驱动液晶分子显示 在第一像素单元中的灰度级与第二像素单元中的灰度级相反。
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公开(公告)号：US20140160111A1
公开(公告)日：2014-06-12
申请号：US14066761
申请日：2013-10-30
Inventor： Liang Zhang , Xibin Shao , Dan Wang , Weihao Hu , Yizhen Xu , Shuai Hou
IPC: H04N13/04
CPC classification number: H04N13/398 , G09G3/003 , G09G3/3677 , G09G2310/0224 , G09G2310/0281 , G09G2320/0209
Abstract: According to embodiments of the present invention, the gate lines of the array substrate receive the gate scanning signal in a preset time period. Specifically, the gate lines of pixel units in odd rows are receiving the gate scanning signal in the first time interval of the preset time period, and the gate lines of pixel units in even rows are receiving the gate scanning signal in the second time interval of the preset time period.
Abstract translation: 根据本发明的实施例，阵列基板的栅极线在预定时间段内接收栅极扫描信号。 具体地说，奇数行中的像素单位的栅极线在预设时间段的第一时间间隔内接收栅极扫描信号，偶数行中的像素单元的栅极线在第二时间间隔中接收栅极扫描信号 预设时间段。
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公开(公告)号：US12197085B2
公开(公告)日：2025-01-14
申请号：US18326208
申请日：2023-05-31
Inventor： Feifei Wang , Hongming Zhan , Xibin Shao , Lintao Ji , Bowen Li
IPC: G02F1/1337 , G02F1/1333 , G02F1/13363
Abstract: A liquid crystal display panel includes a first and second base substrates, a liquid crystal layer and an optical compensation layer. In the liquid crystal layer, a first alignment film is configured to anchor a part, proximate to the first alignment film, of second liquid crystal molecules, and a second alignment film is configured to anchor a part, proximate to the second alignment film, of the second liquid crystal molecules. In the optical compensation layer, a third alignment film is configured to anchor first liquid crystal molecules proximate to the third alignment film. A direction of orthogonal projections of long axes of the first liquid crystal molecules is parallel to a direction of orthogonal projections of long axes of second liquid crystal molecules anchored by the first and second alignment films. Rubbing directions of the first alignment film, the second alignment film and the third alignment film are the same.
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公开(公告)号：US12189897B2
公开(公告)日：2025-01-07
申请号：US17778975
申请日：2021-06-25
Inventor： Yinlong Zhang , Zhihua Sun , Pengfei Hu , Senwang Li , Yanping Liao , Xibin Shao , Xiaofeng Yin , Jiantao Liu , Kaiming Shi , Jinling Zhang
IPC: G06F3/041
Abstract: The present invention relates to a touch display device, a drive control circuit for the touch display device, and a method for operating the touch display device. The touch display device includes a drive control circuit, the drive control circuit is configured to: in a display phase, provide a common voltage signal to a common electrode in a pixel circuit of the touch display device; in a touch phase, provide a touch drive signal to the common electrode, wherein a ratio of an average value of a high level and a low level of the touch drive signal to a value of the common voltage signal ranges from 0.8 to 1.2.
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公开(公告)号：US20240428717A1
公开(公告)日：2024-12-26
申请号：US18826136
申请日：2024-09-05
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
Abstract: There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.
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Patent Agency Ranking
公开(公告)号：US12038643B2
公开(公告)日：2024-07-16
申请号：US18195323
申请日：2023-05-09
Inventor： Xiaona Liu , Xibin Shao
IPC: G02F1/1335
CPC classification number: G02F1/133514 , G02F1/133512
Abstract: A color filter substrate includes a base substrate, a black matrix layer and a color filter layer. The color filter layer includes a plurality of color photoresist units arranged in an array, the plurality of color photoresist units being formed with a plurality of color photoresist rows, a plurality of first color photoresist columns, a plurality of second color photoresist columns and a plurality of third color photoresist columns, and wherein the color filter layer further includes at least one filling part located between the color photoresist rows and has a thickness equal to that of at least one of the plurality of color photoresist units; and the black matrix layer is disposed between the color filter layer and the base substrate, and includes a plurality of light transmitting windows.
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公开(公告)号：US11899868B2
公开(公告)日：2024-02-13
申请号：US17918593
申请日：2021-10-14
Inventor： Mengjie Wang , Xiaona Liu , Xibin Shao
IPC: G06F3/041 , G06F3/044 , G02F1/1333 , G02F1/1343 , G02F1/1362 , H01L27/12
CPC classification number: G06F3/0412 , G02F1/1362 , G02F1/13338 , G02F1/134309 , G02F1/136286 , G06F3/041 , G06F3/0443 , G06F3/0446 , G06F3/04164 , G06F3/04184 , H01L27/124 , G06F2203/04103 , G09G2300/04 , G09G2300/0404 , G09G2300/0426
Abstract: An array substrate includes multiple pixel electrodes constituting first pixel electrode columns, second pixel electrode columns and third pixel electrode columns, and data lines including first data lines, second data lines and third data lines. A first data line, a first pixel electrode column, a second data line, a second pixel electrode column, a third data line and a third pixel electrode column are arranged in sequence in a row direction. Distances between the first pixel electrode column and the first data line, between the second pixel electrode column and the second data line, between the third pixel electrode column and the third data line, and between the first pixel electrode column and the second data line are a first distance to a fourth distance, respectively. The first distance is less than the fourth distance and greater than the second distance and/or the third distance.
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公开(公告)号：US11749161B2
公开(公告)日：2023-09-05
申请号：US18082691
申请日：2022-12-16
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2300/08 , G09G2310/0243 , G09G2310/0267 , G09G2310/0286 , G09G2310/08
Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
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公开(公告)号：US20230215320A1
公开(公告)日：2023-07-06
申请号：US18182479
申请日：2023-03-13
Inventor： Zhihua Sun , Yinlong Zhang , Qiujie Su , Feng Qu , Jing Liu , Yanping Liao , Xibin Shao
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/08 , G09G2310/0278 , G09G2310/0205
Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.
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公开(公告)号：US20220084451A1
公开(公告)日：2022-03-17
申请号：US17341756
申请日：2021-06-08
Inventor： Zhihua Sun , Yinlong Zhang , Qiujie Su , Feng Qu , Jing Liu , Yanping Liao , Xibin Shao
IPC: G09G3/20
Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.
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