公开(公告)号：US09619377B2

公开(公告)日：2017-04-11

申请号：US14458949

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06 ,  G06F1/32

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US09549373B2

公开(公告)日：2017-01-17

申请号：US14444198

申请日：2014-07-28

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Gilbert H. Herbeck

IPC: H04M1/00 ,  H04W52/02

CPC classification number: H04W52/0235 ,  H04W52/0212 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/26

Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.

Abstract translation: 一种用于管理系统中的电力的方法，其中所述系统可以包括被配置为传送串行数据的第一设备和耦合到所述第一设备的第二设备。 第二设备可以包括收发器和中断逻辑，并且可以被配置为激活中断逻辑并使能收发器的降低的功率模式。 以降低功率模式工作的收发器的功耗可能小于工作模式下收发器的功耗。 第二设备还可以被配置为响应于第二设备的输入的电压电平的变化来断言中断信号，然后响应于断言中断信号的断言而使得收发器的降低功率模式被去激活。

公开(公告)号：US20160313396A1

公开(公告)日：2016-10-27

申请号：US14693116

申请日：2015-04-22

Applicant: Apple Inc.

Inventor： James D. Ramsay ,  Manu Gulati ,  Mitchell Palmer Lichtenberg, JR.

IPC: G01R31/3177

CPC classification number: G01R31/31705 ,  G06F11/2221

Abstract: An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.

Abstract translation: 提供一种具有用于与调试器进行接口的桥接器及其操作方法的集成电路（IC）。 在一个实施例中，IC包括在其上实现的调试控制电路和调试接口块（DIB）。 DIB耦合到调试控制电路。 IC还包括用于调试器的接口和用于外部电路的多个接口，每个接口耦合到调试控制电路。 调试控制电路可以用作用于将外部调试器耦合到DIB的桥，以及通过相应的接口耦合到IC的外部电路。 调试控制电路可以建立调试器和其中一个外部电路之间的连接。 调试器和外部电路之间的通信可以绕过DIB进行。

公开(公告)号：US20160240193A1

公开(公告)日：2016-08-18

申请号：US14621093

申请日：2015-02-12

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Gilbert H. Herbeck ,  Alexei E. Kosut ,  Girault W. Jones ,  Timothy J. Millet

IPC: G10L15/28 ,  G10L19/00 ,  G10L15/22

CPC classification number: G10L15/28 ,  G10L15/08 ,  G10L15/22 ,  G10L2015/088 ,  G10L2015/223

Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）可以包括一个或多个中央处理单元（CPU），存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 该电路可以被配置为接收音频采样并将这些音频样本与预定模式相匹配。 在SOC的其余部分断电的时间内，电路可以根据第一时钟进行操作。 响应于检测样本中的预定模式，电路可以使存储器控制器和处理器加电。 在上电过程中，具有比第一时钟具有一个或多个更好特征的第二时钟可以变得可用。 电路可以切换到第二时钟，同时保持采样，或者丢失至多一个采样，或者不超过阈值数量的采样。

公开(公告)号：US20160054773A1

公开(公告)日：2016-02-25

申请号：US14466205

申请日：2014-08-22

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Parin Patel ,  Keith Cox ,  Derek Iwamoto ,  Cyril de la Cropte de Chanterac ,  Christopher J. Young

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.

Abstract translation: 公开了一种用于提供用于功率控制功能的遥测的方法和装置。 一种系统包括具有第一电源管理电路的集成电路（IC）。 IC还包括多个不同功率域内的多个功能电路块。 第二电源管理电路在IC外部实现并且包括多个电压调节器。 每个电源域被耦合以从一个电压调节器接收电力。 在操作期间，第一电源管理电路可以发送请求改变提供给IC的一个或多个电压的命令。 第二电力管理电路可以通过执行所请求的电压变化来响应，并且还可以向第一电力管理电路提供遥测数据。 第二电力管理电路还可以响应于从第一电力管理电路接收无操作命令来提供遥测数据。

公开(公告)号：US09229894B2

公开(公告)日：2016-01-05

申请号：US13859000

申请日：2013-04-09

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S Saund ,  Joseph P Bratt ,  Kevin C Wong ,  Manu Gulati ,  Rohit K Gupta

IPC: G06F13/42 ,  G06F3/00 ,  G06F13/36 ,  G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 第二总线可以包括多个虚拟通道。 桥接电路可以被配置为通过第一总线接收事务，并将事务转换为第二通信协议，并将转换的事务分配给多个虚拟通道中的一个。 可以进一步配置桥接电路来存储转换的事务。 取决于多个虚拟信道的可用信用数量，桥电路可以产生多个有限吞吐量信号。

公开(公告)号：US20150346001A1

公开(公告)日：2015-12-03

申请号：US14458885

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

IPC: G01D9/00 ,  G06F1/32 ,  G06F13/16

CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：US20150143044A1

公开(公告)日：2015-05-21

申请号：US14081549

申请日：2013-11-15

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

公开(公告)号：US09009377B2

公开(公告)日：2015-04-14

申请号：US13666132

申请日：2012-11-01

Applicant: Apple Inc.

Inventor： Erik P Machnicki ,  Deniz Balkan ,  Manu Gulati

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.

Abstract translation: 在一个实施例中，系统包括中断控制器，耦合到中断控制器的一个或多个CPU，通信结构，被配置为产生要发送到中断控制器的中断的一个或多个外围设备，以及一个或多个中断消息电路耦合 到外围设备。 中断消息电路被配置为产生中断消息，以将中断通过结构传送到中断控制器。 一些中断是电平敏感中断，并且中断消息电路被配置为向中断控制器发送电平敏感中断消息。 至少有一个中断是边沿触发的。 该系统配置为将边沿触发中断转换为电平敏感中断，以便可以以相同的方式处理中断。

公开(公告)号：US20140337649A1

公开(公告)日：2014-11-13

申请号：US13890306

申请日：2013-05-09

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Pulkit Desai ,  Rong Zhang Hu

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。