公开(公告)号：US09182811B2

公开(公告)日：2015-11-10

申请号：US13719535

申请日：2012-12-19

Applicant: Apple Inc.

Inventor： Erik P Machnicki ,  Gurjeet S Saund ,  Munetoshi Fukami ,  Shane J Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M Kassoff ,  Kevin C Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

公开(公告)号：US09152588B2

公开(公告)日：2015-10-06

申请号：US13653151

申请日：2012-10-16

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Erik P Machnicki ,  Deniz Balkan

IPC: G06F13/24 ,  G06F13/26

CPC classification number: G06F13/24 ,  G06F13/26 ,  Y02D10/14

Abstract: In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

Abstract translation: 在一个实施例中，系统包括耦合到外围设备的至少一个外围设备，中断控制器，存储器控制器，至少一个CPU以及中断消息电路。 中断消息电路可以被耦合以从外围设备接收中断信号，并且可以被配置为生成用于在通信结构上传输的中断消息。 在一些实施例中，可以存在多个外围设备，其具有通过该结构的独立路径，用于存储器操作到存储器控制器。 每个这样的外设可以耦合到中断消息电路的一个实例。 在一个实施例中，中断是电平敏感的。 中断消息电路可以被配置为向中断控制器发送中断设置消息中断清除消息以指示电平。

公开(公告)号：US09009377B2

公开(公告)日：2015-04-14

申请号：US13666132

申请日：2012-11-01

Applicant: Apple Inc.

Inventor： Erik P Machnicki ,  Deniz Balkan ,  Manu Gulati

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.

Abstract translation: 在一个实施例中，系统包括中断控制器，耦合到中断控制器的一个或多个CPU，通信结构，被配置为产生要发送到中断控制器的中断的一个或多个外围设备，以及一个或多个中断消息电路耦合 到外围设备。 中断消息电路被配置为产生中断消息，以将中断通过结构传送到中断控制器。 一些中断是电平敏感中断，并且中断消息电路被配置为向中断控制器发送电平敏感中断消息。 至少有一个中断是边沿触发的。 该系统配置为将边沿触发中断转换为电平敏感中断，以便可以以相同的方式处理中断。

公开(公告)号：US09413353B2

公开(公告)日：2016-08-09

申请号：US14275473

申请日：2014-05-12

Applicant: Apple Inc.

Inventor： Erik P Machnicki

IPC: H03K19/003 ,  H03K17/14 ,  G05B13/02 ,  G01K3/00

CPC classification number: H03K19/00369 ,  G05B13/021 ,  H03K17/14 ,  Y10T307/773

Abstract: A method and apparatus for thermal voltage margin recovery is disclosed. In one embodiment, an integrated circuit (IC) includes first and second temperature sensors at first and second locations of the IC, respectively. The IC further includes a power management circuit coupled to receive temperature readings from the first and second temperature sensors. Based on received temperature readings, the power management circuit may determine a voltage offset value. The power management circuit may then reduce the operating voltage of the IC by the voltage offset value.

Abstract translation: 公开了一种用于热电压裕度恢复的方法和装置。 在一个实施例中，集成电路（IC）分别在IC的第一和第二位置处包括第一和第二温度传感器。 IC还包括电源管理电路，其耦合以接收来自第一和第二温度传感器的温度读数。 基于所接收的温度读数，功率管理电路可以确定电压偏移值。 然后，电源管理电路可以通过电压偏移值来降低IC的工作电压。

公开(公告)号：US09310783B2

公开(公告)日：2016-04-12

申请号：US13719517

申请日：2012-12-19

Applicant: Apple Inc.

Inventor： Erik P Machnicki ,  Gurjeet S Saund ,  Munetoshi Fukami ,  Shane J Keil

IPC: G05B11/01 ,  G06F1/32

CPC classification number: G05B11/01 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract translation: 公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。 在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。 每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。 功率管理单元可以通过使请求功能单元进入低功率状态来进行响应。 如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。 接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。

公开(公告)号：US09152210B2

公开(公告)日：2015-10-06

申请号：US13767897

申请日：2013-02-15

Applicant: Apple Inc.

Inventor： Erik P Machnicki ,  Brian P Lilly ,  Gurjeet S Saund ,  Sukalpa Biswas

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Various method and apparatus embodiments for selecting tunable operating parameters in an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a number of various functional blocks each having a local management circuit. The IC also includes a global management unit coupled to each of the functional blocks having a local management circuit. The management unit is configured to determine the operational state of the IC based on the respective operating states of each of the functional blocks. Responsive to determining the operational state of the IC, the management unit may provide indications of the same to the local management circuit of each of the functional blocks. The local management circuit for each of the functional blocks may select one or more tunable parameters based on the operational state determined by the management unit.

Abstract translation: 公开了用于在集成电路（IC）中选择可调工作参数的各种方法和装置实施例。 在一个实施例中，IC包括多个各自具有本地管理电路的功能块。 IC还包括耦合到具有本地管理电路的每个功能块的全局管理单元。 管理单元被配置为基于每个功能块的各自的操作状态来确定IC的操作状态。 响应于确定IC的操作状态，管理单元可以向每个功能块的本地管理电路提供相同的指示。 每个功能块的本地管理电路可以基于由管理单元确定的操作状态来选择一个或多个可调参数。