公开(公告)号：US20080137443A1

公开(公告)日：2008-06-12

申请号：US11941101

申请日：2007-11-16

Applicant: Dong Hyuk CHAE ,  Young Ho LIM

Inventor： Dong Hyuk CHAE ,  Young Ho LIM

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

Abstract: A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the man data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

Abstract translation: 提供一种包括存储器阵列，页缓冲器和行解码器的非易失性半导体存储器件。 存储器阵列包括多个非易失性存储器单元，位线和字线，并且行解码器被驱动以控制存储器阵列的字线。 页缓冲器电连接到位线，并包括主数据锁存器和子数据锁存器。 根据子数据锁存器的逻辑状态禁止翻转人数据锁存器的页缓冲器还包括主锁存块，子锁存块和锁存控制块。 主锁存块驱动主数据锁存器，并通过位线将主数据锁存器的逻辑状态映射到相应存储器单元的阈值电压。 子锁存块驱动子数据锁存器，其中子数据锁存器根据位线的电压电平翻转。 锁存控制块根据位线的电压电平有选择地翻转主数据锁存器，根据子数据锁存器的逻辑状态，禁止锁存器控制块。

公开(公告)号：US07362612B2

公开(公告)日：2008-04-22

申请号：US11598090

申请日：2006-11-13

Applicant: Sang-gu Kang ,  Young-Ho Lim

Inventor： Sang-gu Kang ,  Young-Ho Lim

IPC: G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3459

Abstract: The invention provides a programming method for a flash memory device including first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method may include programming memory cells, connected with a selected row and the second bitlines, with multi-bit data; determining whether the selected row is the last row; and reprogramming programmed memory cells connected with the selected row being the last row and the first bitlines when the determination result is that the selected row is the last row.

Abstract translation: 本发明提供了一种用于闪存器件的编程方法，其包括与多个存储器单元连接的第一和第二位线，用于存储指示多个状态之一的多位数据。 程序方法可以包括利用多位数据来编程与所选择的行和第二位线连接的存储器单元; 确定所选行是否是最后一行; 并且当确定结果是所选择的行是最后一行时，与所选行连接的编程存储器单元重新编程为最后一行和第一位。

公开(公告)号：US20080025090A1

公开(公告)日：2008-01-31

申请号：US11870528

申请日：2007-10-11

Applicant: Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

Inventor： Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

Abstract translation: 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US07298654B2

公开(公告)日：2007-11-20

申请号：US11133234

申请日：2005-05-20

Applicant: Jae-Yong Jeong ,  Young-Ho Lim

Inventor： Jae-Yong Jeong ,  Young-Ho Lim

IPC: G11C11/34

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract translation: 公开了一种非易失性存储器件和擦除非易失性存储器件的方法。 同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。 然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。 根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。 在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

公开(公告)号：US20070183210A1

公开(公告)日：2007-08-09

申请号：US11700834

申请日：2007-02-01

Applicant: Ki-Hwan Choi ,  Young-Ho Lim

Inventor： Ki-Hwan Choi ,  Young-Ho Lim

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: The present invention provides a program method of a flash memory device including a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although a threshold voltage distribution is widened due to an electric field coupling/F-poly coupling and HTS, a read margin between adjacent states may be sufficiently secured using the program method.

Abstract translation: 本发明提供了一种闪速存储装置的编程方法，其包括用于存储指示多个状态之一的多位数据的多个存储单元。 对存储器单元进行主程序操作。 布置在各个状态的特定区域内的那些存储单元经受二次编程操作，以具有等于或高于在主程序操作中使用的验证电压的阈值电压。 因此，尽管由于电场耦合/ F-poly耦合和HTS而使阈值电压分布变宽，但是可以使用编程方法充分确保相邻状态之间的读取余量。

公开(公告)号：US07227790B2

公开(公告)日：2007-06-05

申请号：US11263716

申请日：2005-11-01

Applicant: Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

Inventor： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC: G11C7/06

CPC classification number: G11C16/26

Abstract: In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

Abstract translation: 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20070076497A1

公开(公告)日：2007-04-05

申请号：US11317303

申请日：2005-12-27

Applicant: Dong Hyuk Chae ,  Young Ho Lim

Inventor： Dong Hyuk Chae ,  Young Ho Lim

IPC: G11C7/02

CPC classification number: G11C7/1027 ,  G11C29/84

Abstract: A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresponding to an embedded address, and generating a redundancy flag signal, such that the embedded address is an address preceding the address of the memory cell of the normal cell array to be repaired by at least one clock.

公开(公告)号：US20070074194A1

公开(公告)日：2007-03-29

申请号：US11439797

申请日：2006-05-24

Applicant: Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

Inventor： Wook-Ghee Hahn ,  Young-Ho Lim ,  Dae-Seok Byeon

IPC: G06F9/45

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202

Abstract: A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells. Related devices are also discussed.

Abstract translation: 包括多个存储器单元的非易失性存储器件的编程方法包括提供具有与其相关联的相应多个编程电压的多个程序循环。 多个程序循环中的第一个被激活以产生第一编程电压以编程多个存储器单元中的第一个。 多个程序循环中的第二个程序循环被激活以产生第二编程电压以编程多个存储器单元中的第二个。 还讨论了相关设备。

公开(公告)号：US20070070701A1

公开(公告)日：2007-03-29

申请号：US11500410

申请日：2006-08-08

Applicant: Moo-Sung Kim ,  Young-Ho Lim

Inventor： Moo-Sung Kim ,  Young-Ho Lim

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C8/08 ,  G11C16/0483

Abstract: A NAND flash memory device and a programming method thereof capable of improving a program speed during a multi-level cell programming operation are provided. The device performs a programming operation using an ISPP method. Additionally, the device includes a memory cell storing multi-bit data; a program voltage generating circuit generating a program voltage to be supplied to the memory cell; and a program voltage controller controlling a start level of the program voltage. The device supplies an LSB start voltage to a selected word line during an LSB program, and an MSB start voltage higher than the LSB start voltage to the selected word line during an MSB program.

Abstract translation: 提供一种能够在多级单元编程操作期间提高编程速度的NAND快闪存储器件及其编程方法。 该设备使用ISPP方法执行编程操作。 另外，该设备包括存储多位数据的存储单元; 编程电压产生电路，产生要提供给存储单元的编程电压; 以及控制编程电压的起始电平的编程电压控制器。 在MSB程序期间，器件在LSB程序期间将LSB起始电压提供给所选择的字线，并在MSB程序期间向所选字线提供高于LSB起始电压的MSB启动电压。

公开(公告)号：US06914814B2

公开(公告)日：2005-07-05

申请号：US10630116

申请日：2003-07-30

Applicant: Jae-woo Im ,  Young-ho Lim

Inventor： Jae-woo Im ,  Young-ho Lim

IPC: G11C16/06 ,  G11C7/00 ,  G11C11/34 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/82 ,  G11C29/846 ,  G11C2216/22

Abstract: A flash memory device can include a first redundancy circuit configured to provide read repair information for read operations to the flash memory. The flash memory device can also include a second redundancy circuit, separate from the first redundancy circuit, configured to provide write repair information for write operations to the flash memory. The flash memory device can include a dedicated-read operation redundancy circuit configured to provide read repair information and a dedicated-write operation redundancy circuit configured to provide write repair information. The flash memory device can include also include a first redundancy circuit configured to store an address of a defective memory cell in the flash memory and a second redundancy circuit, separate from the first redundancy circuit, configured to store the address of the defective memory cell.

Abstract translation: 闪存器件可以包括被配置为向闪存提供用于读取操作的读取修复信息的第一冗余电路。 闪存器件还可以包括与第一冗余电路分离的第二冗余电路，其被配置为向闪存提供用于写入操作的写入修复信息。 闪存器件可以包括被配置为提供读修复信息的专用读操作冗余电路和被配置为提供写修复信息的专用写操作冗余电路。 闪存器件还可以包括第一冗余电路，其被配置为将闪存中的有缺陷的存储器单元的地址存储在存储器中，并且与第一冗余电路分离的第二冗余电路被配置为存储有缺陷的存储器单元的地址。