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公开(公告)号：US20220191144A1
公开(公告)日：2022-06-16
申请号：US17383755
申请日：2021-07-23
发明人： Morten Terstrup
IPC分类号： H04L12/851 , H04L12/841 , H04L12/863 , H04L12/935 , H04L12/743
摘要： A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.
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公开(公告)号：US11341304B2
公开(公告)日：2022-05-24
申请号：US17111218
申请日：2020-12-03
IPC分类号： G06F30/343 , G06F119/12 , G06N3/08
摘要： A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.
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公开(公告)号：US11271712B2
公开(公告)日：2022-03-08
申请号：US16827624
申请日：2020-03-23
发明人： Thomas Joergensen , Brian Branscomb
IPC分类号： H04L7/00 , H04L12/931 , H04L49/351
摘要： A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.
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84.发明申请公开(公告)号：US20220027083A1
公开(公告)日：2022-01-27
申请号：US17089891
申请日：2020-11-05
发明人： Lorenzo Zuolo , Rino Micheloni
摘要： A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.
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公开(公告)号：US11222782B2
公开(公告)日：2022-01-11
申请号：US16785491
申请日：2020-02-07
IPC分类号： H01L21/02 , H01L21/04 , H01L27/092 , H01L21/67
摘要： A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.
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公开(公告)号：US20210211267A1
公开(公告)日：2021-07-08
申请号：US16827624
申请日：2020-03-23
发明人： Thomas JOERGENSEN , Brian BRANSCOMB
IPC分类号： H04L7/00 , H04L12/931
摘要： A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.
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公开(公告)号：US10972249B1
公开(公告)日：2021-04-06
申请号：US17022480
申请日：2020-09-16
摘要： A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine.
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88.发明授权公开(公告)号：US10972084B1
公开(公告)日：2021-04-06
申请号：US16867468
申请日：2020-05-05
摘要： A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.
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公开(公告)号：US10819318B1
公开(公告)日：2020-10-27
申请号：US16595096
申请日：2019-10-07
发明人： Barry Britton , Phillip Johnson , John Schadt , David Onimus
IPC分类号： H03K3/356 , H03K3/037 , G11C11/4078 , H03K19/003 , G06F1/14 , H03K5/133
摘要： An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.
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公开(公告)号：US20200327937A1
公开(公告)日：2020-10-15
申请号：US16405895
申请日：2019-05-07
发明人： Victor Nguyen , Fethi Dhaoui , John L. McCollum , Fengliang Xue
摘要： A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
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