公开(公告)号：US20210173993A1

公开(公告)日：2021-06-10

申请号：US17111218

申请日：2020-12-03

申请人： Microchip Technology Inc.

发明人： Madhusudan Raman ,  Nizar Abdallah ,  Julien G. Dunoyer

IPC分类号： G06F30/343 ,  G06N3/08

摘要： A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.

公开(公告)号：US11341304B2

公开(公告)日：2022-05-24

申请号：US17111218

申请日：2020-12-03

申请人： Microchip Technology Inc.

发明人： Madhusudan Raman ,  Nizar Abdallah ,  Julien G. Dunoyer

IPC分类号： G06F30/343 ,  G06F119/12 ,  G06N3/08

摘要： A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.