Method and apparatus for carrying constant bit rate (CBR) client signals

    公开(公告)号:US11799626B2

    公开(公告)日:2023-10-24

    申请号:US17885194

    申请日:2022-08-10

    IPC分类号: H04L7/04 H04J3/06 H04L12/70

    摘要: A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

    System and method for low latency network switching

    公开(公告)号:US11658911B2

    公开(公告)日:2023-05-23

    申请号:US17383755

    申请日:2021-07-23

    发明人: Morten Terstrup

    摘要: A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.

    Redundant angular position sensor and associated method of use

    公开(公告)号:US11656101B2

    公开(公告)日:2023-05-23

    申请号:US17146875

    申请日:2021-01-12

    发明人: Ganesh Shaga

    IPC分类号: G01D5/20 G01B7/30

    CPC分类号: G01D5/2073 G01B7/30

    摘要: A redundant angular position sensor comprising a first angular position sensor including a first excitation coil, a first sensing coil and a second sensing coil and a second angular position sensor. The second angular position sensor including a second excitation coil, a third sensing coil and a fourth sensing coil. Each of the first, second, third and fourth sensing coils comprising a respective clockwise winding portion and a respective counter-clockwise winding portion. The redundant angular position sensor further comprises a rotatable inductive coupling element positioned in overlying relation to the sensing coils and separated from the sensing coils by a gap, wherein the rotatable inductive coupling element comprises four, substantially evenly radially spaced, sector apertures.

    SYSTEM AND METHOD FOR BYPASS MEMORY READ REQUEST DETECTION

    公开(公告)号:US20220382688A1

    公开(公告)日:2022-12-01

    申请号:US17741282

    申请日:2022-05-10

    IPC分类号: G06F13/16 G06F13/42 G06F11/10

    摘要: System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

    System of Multiple Stacks in a Processor Devoid of an Effective Address Generator

    公开(公告)号:US20220342668A1

    公开(公告)日:2022-10-27

    申请号:US17468574

    申请日:2021-09-07

    IPC分类号: G06F9/30 G06F9/38

    摘要: In one implementation devoid of an effective address generator a method of call operation comprises pushing one or more parameters onto a first stack, pushing the contents of one or more registers onto a second stack, popping off the first stack one or more of the parameters into one or more of the registers whose contents were pushed onto the second stack, performing register to register operations on the one or more registers whose contents were pushed onto the second stack with a result of the register to register operations being stored in a result register, the result register being one of the one or more registers whose contents were pushed onto the second stack, popping off the second stack the contents of all the one or more registers into their respective registers from which they came, and returning control to an instruction following the call.

    SYSTEM AND METHOD FOR DOUBLE DATA RATE (DDR) CHIP-KILL RECOVERY

    公开(公告)号:US20220342582A1

    公开(公告)日:2022-10-27

    申请号:US17671423

    申请日:2022-02-14

    IPC分类号: G06F3/06

    摘要: A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.

    HIGH RESOLUTION ANGULAR INDUCTIVE SENSOR AND ASSOCIATED METHOD OF USE

    公开(公告)号:US20220187335A1

    公开(公告)日:2022-06-16

    申请号:US17359694

    申请日:2021-06-28

    发明人: Ganesh Shaga

    IPC分类号: G01P3/488 G01D5/20

    摘要: An angular position sensor comprising two annular sensors, one annular sensor for generating a coarse resolution time varying signal in the presence of a rotatable inductive coupling element and the other annular sensor for generating a fine resolution time varying signal in the presence of the rotatable inductive coupling element. The rotatable inductive coupling element comprising a first annular portion comprising at least one annular conductive sector and at least one annular non-conductive sector and a second annular portion comprising at least one annular conductive sectors and at least one annular non-conductive sector, wherein the number of annular conductive sectors of the first annular portion and the second annular portion are different. In particular, the annular conductive sectors of the annular portions may comprise 50% or 75% of the total area of the annular portions.

    Method for erasing a ReRAM memory cell

    公开(公告)号:US11355187B2

    公开(公告)日:2022-06-07

    申请号:US17140064

    申请日:2021-01-02

    IPC分类号: G11C13/00 H01L45/00

    摘要: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.