公开(公告)号：US06346455B1

公开(公告)日：2002-02-12

申请号：US09651946

申请日：2000-08-31

申请人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

发明人： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

IPC分类号： H01L2120

CPC分类号： H01L28/87 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprising a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch resistant material, and etching the alternating layers thereby forming a capacitor structure having corrugated sides.

摘要翻译： 一种在半导体部件上形成波纹状电容器的方法。 形成波纹状电容器的方法包括在半导体组件上具有不同蚀刻速率的一系列沉积交替层的掺杂硅玻璃，用抗蚀刻材料覆盖交替层，并且蚀刻交替层，从而形成具有波纹状的电容器结构 。

公开(公告)号：US06274423B1

公开(公告)日：2001-08-14

申请号：US09236761

申请日：1999-01-25

申请人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

发明人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

摘要翻译： 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 该蚀刻工艺在形成于半导体衬底上的电容器结构中实施。电容器结构包括第一导体，第一导体上的电介质层和介电层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

公开(公告)号：US06211007B1

公开(公告)日：2001-04-03

申请号：US08868058

申请日：1997-06-03

申请人： Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

发明人： Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

IPC分类号： H01L218242

CPC分类号： H01L27/10852

摘要： A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

摘要翻译： 一种用于增强动态随机存取存储器中的刷新的过程，其中在形成存取晶体管部件之后，将n型杂质注入到电容器埋入接触中。 该工艺包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成晶体管栅电极。 第一和第二晶体管源极/漏极区域形成在与栅电极的相对侧相邻的衬底上。 然后将N型杂质（优选磷原子）注入到用作电容器掩埋接触的第一源极/漏极区域中。

公开(公告)号：US6127236A

公开(公告)日：2000-10-03

申请号：US131454

申请日：1998-08-10

申请人： Kirk D. Prall ,  Mike P. Violette

发明人： Kirk D. Prall ,  Mike P. Violette

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735

CPC分类号： H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

摘要： A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

摘要翻译： 基本同心的横向双极晶体管及其形成方法。 基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。 栅极覆盖基板和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US5976985A

公开(公告)日：1999-11-02

申请号：US911311

申请日：1997-08-14

申请人： Kevin G. Donohoe ,  Kirk D. Prall

发明人： Kevin G. Donohoe ,  Kirk D. Prall

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/465

CPC分类号： H01L21/31116 ,  H01L21/76804

摘要： Methods of forming contact openings over a node location and related integrated circuitry are described. In one aspect of the invention, a node location is formed within a semiconductive substrate adjacent an isolation oxide region. A layer of material is formed over the node location and a contact opening is etched through the layer of material to outwardly expose a node location planar upper surface. In one preferred implementation, the contact opening includes an inner surface portion which faces generally transversely away from the isolation oxide region and which defines an angle with the node location upper surface which is greater at a bottom of the contact opening than at a top of the contact opening. In another preferred implementation, the contact opening includes sidewall portions which define a profile which having a non-uniform degree of taper between the contact opening top and bottom. In another preferred implementation, the tapering of the contact opening is effectuated by modifying at least one etching parameter at an intermediate etching point and continuing the etching to outwardly expose the node location.

公开(公告)号：US5728596A

公开(公告)日：1998-03-17

申请号：US733506

申请日：1996-10-18

申请人： Kirk D. Prall

发明人： Kirk D. Prall

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S438/947

摘要： A removable oxide spacer is used to reduce the size of a contact opening in a DRAM cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that if fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. Etching of the spacer creates a buried contact opening smaller than lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after resist strip leaving a sublithographic buried contact opening.

摘要翻译： 使用可去除的氧化物间隔物来减小在低于光刻最小值的多晶硅字线之间的DRAM单元中的接触开口的尺寸。 可去除的间隔物在掩埋接触图案化和蚀刻之前被沉积。 由于字线在单元位置发散，所以可拆卸间隔物在发散区域接触开口之间保持较小的厚度，并且由于其间较窄的间隙而在字线之间的其他位置具有更大的厚度，并且间隔物被沉积，使得如果填充间隙。 由于实际的自对准接触区域由间隔壁侧壁限定，所以可拆卸间隔物减小了埋入接触尺寸。 间隔物的蚀刻产生小于光刻最小值的埋入接触开口，因为围绕埋入接触区域的氧化硅被可移除间隔物保护。 在抗蚀剂条带离开亚光刻掩埋的接触开口之后，去除可移除的间隔物。

公开(公告)号：US5650349A

公开(公告)日：1997-07-22

申请号：US399843

申请日：1995-03-07

申请人： Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

发明人： Kirk D. Prall ,  Robert Kerr ,  Christopher Murphy ,  D. Mark Durcan

IPC分类号： H01L21/8242 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852

摘要： A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

摘要翻译： 一种用于增强动态随机存取存储器中的刷新的过程，其中在形成存取晶体管部件之后，将n型杂质注入到电容器埋入接触中。 该工艺包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成晶体管栅电极。 第一和第二晶体管源极/漏极区域形成在与栅电极的相对侧相邻的衬底上。 然后将N型杂质（优选磷原子）注入到用作电容器掩埋接触的第一源极/漏极区域中。

公开(公告)号：US09099314B2

公开(公告)日：2015-08-04

申请号：US12827506

申请日：2010-06-30

申请人： Gurtej S. Sandhu ,  Kirk D. Prall

发明人： Gurtej S. Sandhu ,  Kirk D. Prall

IPC分类号： H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3205

CPC分类号： H01L21/67063 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32053 ,  H01L21/32134

摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

摘要翻译： 在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。 相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。 选择性地去除未反应部分以留下独立间隔物的图案。 独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

公开(公告)号：US08395140B2

公开(公告)日：2013-03-12

申请号：US12833314

申请日：2010-07-09

申请人： Nirmal Ramaswamy ,  Kirk D. Prall

发明人： Nirmal Ramaswamy ,  Kirk D. Prall

IPC分类号： H01L45/00

CPC分类号： H01L45/14 ,  G11C13/0004 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145

摘要： Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.

摘要翻译： 利用存储单元的存储器件，其中包括电阻元件和耦合在两个导体之间的二极管。 二极管包括钌材料和硅材料。 二极管还包括硅材料上的钌或钌化硅的界面。 硅化钌界面可以是多晶硅化钌。

公开(公告)号：US20120074373A1

公开(公告)日：2012-03-29

申请号：US12893992

申请日：2010-09-29

申请人： D.V. Nirmal Ramaswamy ,  Kirk D. Prall

发明人： D.V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC分类号： H01L45/00

CPC分类号： H01L45/14 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

摘要： Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

摘要翻译： 一些实施例包括具有串联连接的两个电容器的电子设备。 两个电容器共享一个公共电极。 电容器中的一个包括半导体衬底的区域和这种区域与公共电极之间的电介质。 电容器中的另一个包括在第二电极和公共电极之间的第二电极和离子传导材料。 第一和第二电极中的至少一个具有直接抵靠离子导电材料的电化学活性表面。 一些实施例包括具有串联连接的两个电容器的存储单元，并且一些实施例包括包含这种存储单元的存储器阵列