公开(公告)号：US07224621B2

公开(公告)日：2007-05-29

申请号：US11515005

申请日：2006-09-05

Applicant: Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C7/10

CPC classification number: G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US20070103958A1

公开(公告)日：2007-05-10

申请号：US11612144

申请日：2006-12-18

Applicant: Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

Inventor： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Abstract translation: 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

公开(公告)号：US20070063400A1

公开(公告)日：2007-03-22

申请号：US10551356

申请日：2004-03-29

Applicant: Katsumi Yamaguchi ,  Hiroshi Nakamura

Inventor： Katsumi Yamaguchi ,  Hiroshi Nakamura

IPC: C21C5/46

CPC classification number: B22F9/082 ,  B22F2009/088 ,  H05K3/3468

Abstract: A metal jet apparatus comprises a discharge nozzle 31 for jetting molten metal 20, and a gas passage 33 for supplying inert gas to a peripheral portion of a discharge port 32 of the discharge nozzle 31. The discharge port 32 of the discharge nozzle 31 and an outlet of a gas passage 33 are provided with a nozzle cover 34. The nozzle cover 34 includes a space 35 which is in communication with the discharge port 32 and the outlet of the gas passage 33, and which opens downward. A ring-like projection 36 is disposed around the opening. When the molten metal 20 is jetted from the discharge port 32 into the space 35, the inert gas is supplied to the space 35, thereby preventing the molten metal 20 from being oxidized, and it is possible to prevent the nozzle of the discharge port 32 from being clogged, and to form the molten metal 20 into a spherical shape.

Abstract translation: 金属喷射装置包括用于喷射熔融金属20的排出喷嘴31和用于向排出喷嘴31的排出口32的周边部分供给惰性气体的气体通道33。 排出喷嘴31的排出口32和气体通道33的出口设置有喷嘴盖34。 喷嘴盖34包括与排出口32和气体通道33的出口连通并且向下开口的空间35。 环形突起36设置在开口周围。 当熔融金属20从排出口32喷射到空间35中时，惰性气体被供应到空间35，从而防止熔融金属20被氧化，并且可以防止排出口32的喷嘴 从而被堵塞，并将熔融金属20形成为球形。

公开(公告)号：US07187225B2

公开(公告)日：2007-03-06

申请号：US11201382

申请日：2005-08-11

Applicant: Masaharu Yuhara ,  Yasuhiro Shiraki ,  Kazuhito Okishio ,  Hiroshi Nakamura ,  Hisato Umemaru ,  Yoshimitsu Takahata ,  Yasuaki Gotoh

Inventor： Masaharu Yuhara ,  Yasuhiro Shiraki ,  Kazuhito Okishio ,  Hiroshi Nakamura ,  Hisato Umemaru ,  Yoshimitsu Takahata ,  Yasuaki Gotoh

IPC: H03K5/08

CPC classification number: H02H9/005 ,  H02H9/046

Abstract: This invention provides an electronic control unit is capable of suppressing electromagnetic noise having a frequency band used in a portable wireless apparatus, and capable of exhibiting a noise resistance property against electromagnetic noise. The electronic control unit including a constant voltage power supply circuit portion, an analog signal inputting circuit portion, and a conversion processing circuit portion, an analog sensor and a driving power supply being connected to the outside, and the unit being connected to the analog sensor through a power supply line and a signal line, in which the analog signal inputting circuit portion includes a current limiting circuit portion, an integrating circuit portion, a current limiting resistor, a signal noise absorbing circuit, and a first bypass capacitor, and capacitance (C1) and parasitic inductance (L1) of the first bypass capacitor are set in a range of 7×106

Abstract translation: 本发明提供一种电子控制单元，其能够抑制具有在便携式无线装置中使用的频带的电磁噪声，并且能够表现出抗电磁噪声的抗噪声特性。 电子控制单元包括恒压电源电路部分，模拟信号输入电路部分和转换处理电路部分，模拟传感器和驱动电源连接到外部，并且该单元连接到模拟传感器 通过电源线和信号线，其中模拟信号输入电路部分包括限流电路部分，积分电路部分，限流电阻器，信号噪声吸收电路和第一旁路电容器以及电容（ C 1）和第一旁路电容器的寄生电感（L 1）设定在7×10 6 <1 / [2pi√（L 1x C 1）] <35×10 6的范围内， / SUP>。

公开(公告)号：US20070047360A1

公开(公告)日：2007-03-01

申请号：US11582065

申请日：2006-10-17

Applicant: Koichi Kawai ,  Kenichi Imamiya ,  Hiroshi Nakamura

Inventor： Koichi Kawai ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC: G11C7/02

CPC classification number: G11C16/105 ,  G11C7/1006 ,  G11C7/1021 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/3431 ,  H01L27/115

Abstract: Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

公开(公告)号：US20070016738A1

公开(公告)日：2007-01-18

申请号：US11530551

申请日：2006-09-11

Applicant: Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

Inventor： Koji Hosono ,  Toshihiko Himeno ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC: G06F12/00 ,  G06F13/28 ,  G06F13/00 ,  G06F9/00 ,  G06F15/177 ,  G11C16/06 ,  G11C11/34

CPC classification number: G11C29/789 ,  G11C7/20 ,  G11C16/20 ,  G11C2029/4402

Abstract: A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.

Abstract translation: 非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。 存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。 非易失性半导体存储器还包括初始设置数据锁存器。 在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

公开(公告)号：US07151685B2

公开(公告)日：2006-12-19

申请号：US11330352

申请日：2006-01-12

Applicant: Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

Inventor： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC: G11C5/06 ,  G11C7/00

CPC classification number: G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

公开(公告)号：US07132875B2

公开(公告)日：2006-11-07

申请号：US11139510

申请日：2005-05-31

Applicant: Hiroshi Nakamura

Inventor： Hiroshi Nakamura

IPC: H03K17/16 ,  H03K17/92

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H01L27/088 ,  H01L27/092 ,  H03K17/08142 ,  H03K17/102 ,  H03K17/693 ,  H03K19/00315 ,  H03K19/018521

Abstract: A voltage switching circuit is disclosed which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.

公开(公告)号：US07123526B2

公开(公告)日：2006-10-17

申请号：US11337999

申请日：2006-01-24

Applicant: Kazushige Kanda ,  Koichi Kawai ,  Hiroshi Nakamura ,  Kenichi Imamiya

Inventor： Kazushige Kanda ,  Koichi Kawai ,  Hiroshi Nakamura ,  Kenichi Imamiya

IPC: G11C7/00

CPC classification number: G11C7/1063 ,  G11C7/1051 ,  G11C7/20 ,  G11C16/20 ,  G11C16/30

Abstract: A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.

Abstract translation: 本发明的半导体器件包括：初始化电路，用于根据电源电压的电平初始化预定电路;以及状态设置单元，用于在初始化期间将半导体器件的状态设置为“忙” 电路执行初始化。

公开(公告)号：US20060176928A1

公开(公告)日：2006-08-10

申请号：US11348323

申请日：2006-02-07

Applicant: Hiroshi Nakamura ,  Toshiyuki Kobayashi ,  Shinichiro Hayasaka ,  Seiichi Kaise

Inventor： Hiroshi Nakamura ,  Toshiyuki Kobayashi ,  Shinichiro Hayasaka ,  Seiichi Kaise

IPC: H05B7/18

CPC classification number: H01L21/6719 ,  H01L21/67017

Abstract: A substrate processing apparatus according to the present invention comprises a plurality of processing chambers, discharge systems each provided in conjunction with one of the processing chambers and a common discharge system connected with the discharge systems of at least two processing chambers among the discharge systems provided in conjunction with the individual processing chambers. The common discharge allows a switch-over between a scrubbing common discharge system that discharges discharge gas from each processing chamber after scrubbing the discharge gas at a scrubbing means and a non-scrubbing common discharge system that directly discharges the discharge gas from the discharge system of the processing chamber without scrubbing at the scrubbing means. In this substrate processing apparatus, switch-over control is executed to select either the scrubbing common discharge system of the non-scrubbing common discharge system in correspondence to the type of processing executed in the processing chamber.

Abstract translation: 根据本发明的基板处理装置包括多个处理室，每个排放系统分别与处理室中的一个相连接，以及与排放系统中的至少两个处理室的排放系统连接的公共排放系统 与各个处理室结合。 公共放电允许在洗涤在洗涤装置处的排出气体之后排出来自每个处理室的排出气体的洗涤普通排放系统和从排放系统直接排出排放气体的非洗涤公共排放系统之间的切换 该处理室不在洗涤装置处洗涤。 在该基板处理装置中，执行切换控制，以对应于在处理室中执行的处理的类型来选择非擦洗普通放电系统的擦洗普通放电系统。