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71.发明申请公开(公告)号：US20050129143A1
公开(公告)日：2005-06-16
申请号：US11010020
申请日：2004-12-13
申请人： Kyung Kang , In Choi
发明人： Kyung Kang , In Choi
CPC分类号： H04L25/0222 , H04L25/0202 , H04L25/03057 , H04L2025/03375 , H04L2025/0349 , H04L2025/03694 , H04L2025/03726
摘要： A channel equalizing device and method of a digital broadcasting receiving system in which a digital broadcasting signal received over a channel is compensated for a channel distortion to recover an original signal is provided. The channel equalizing device includes: a channel estimating unit for estimating and outputting a channel impulse response of a signal, which is received over a transmission channel; a channel characteristic detecting unit for determining as to whether a channel characteristic is a dynamic channel or a static channel by using a difference between the channel impulse response estimated at a current time and outputted from the channel estimating unit and the channel impulse response estimated at a previous time; and a channel equalizing unit for controlling a parameter of an internal filter depending on the channel characteristic detected by the channel characteristic detecting unit, to compensate the received signal for the channel distortion.
摘要翻译： 提供一种数字广播接收系统的信道均衡装置和方法，其中通过信道接收的数字广播信号被补偿信道失真以恢复原始信号。 信道均衡装置包括：信道估计单元，用于估计并输出通过传输信道接收的信号的信道脉冲响应; 信道特性检测单元，用于通过使用当前时间估计的并从信道估计单元输出的信道脉冲响应与在信道估计单元估计的信道脉冲响应之间的差异来确定信道特性是动态信道还是静态信道 以前的时间 以及信道均衡单元，用于根据由信道特性检测单元检测的信道特性来控制内部滤波器的参数，以补偿接收到的信道失真信号。
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72.发明授权
公开(公告)号：US6055269A
公开(公告)日：2000-04-25
申请号：US944599
申请日：1997-10-06
申请人： Robert J. Drost , Robert Bosnyak , Jose M. Cruz
发明人： Robert J. Drost , Robert Bosnyak , Jose M. Cruz
CPC分类号： H04L25/03878
摘要： A method and apparatus for providing equalization for a communication channel is provided. The invention uses edge transition samples, such as those obtained for phase detection in a phase locked loop (PLL) circuit, to determine the amount of equalization to be applied to signals received from a communication channel. By monitoring run lengths of consecutive identical bits received from the communication channel, the invention provides equalization for various frequency components present in the receive signal. One embodiment of the invention subtracts a weighted RC-filtered version of the receive signal from the unfiltered receive signal to provide an equalized receive signal. In this embodiment, a control circuit that monitors the received run lengths and edge transition information adjusts the resistance of the RC filter to adapt the equalization to the data being received and the potentially time varying conditions for the communication channel. Other embodiments of the invention use an analog finite impulse response filter, digital finite impulse response filter, analog decision feedback equalizer, digital decision feedback equalizer, analog forward feedback equalizer, or digital forward feedback equalizer to provide equalization based on the same information.
摘要翻译： 提供了一种用于提供通信信道的均衡的方法和装置。 本发明使用诸如在锁相环（PLL）电路中用于相位检测获得的边缘跃迁样本来确定要应用于从通信信道接收的信号的均衡量。 通过监视从通信信道接收的连续相同比特的运行长度，本发明提供了接收信号中存在的各种频率分量的均衡。 本发明的一个实施例从未滤波的接收信号中减去接收信号的加权RC滤波版本，以提供均衡的接收信号。 在本实施例中，监视所接收的行程长度和边沿转换信息的控制电路调整RC滤波器的电阻以使均衡与正被接收的数据和通信信道的潜在时变条件相适应。 本发明的其他实施例使用模拟有限脉冲响应滤波器，数字有限脉冲响应滤波器，模拟判决反馈均衡器，数字判决反馈均衡器，模拟前向反馈均衡器或数字正向反馈均衡器，以基于相同的信息提供均衡。
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73.发明授权Log compressing circuit providing capability of keeping clamp level independent of variety of amplification factor 失效记录压缩电路提供保持钳位电平独立于各种放大因子的能力
公开(公告)号：US5304873A
公开(公告)日：1994-04-19
申请号：US994789
申请日：1992-12-22
申请人： Masanori Inamori , Toshihide Miyake
发明人： Masanori Inamori , Toshihide Miyake
CPC分类号： H03G7/001
摘要： A log compressing circuit is arranged so that the clamping level is independent of the amplification factor of a first transistor for amplifying input current. The log compressing circuit includes the first transistor for amplifying input current, a compressing diode for log-compressing the amplified current, a clamp voltage generating diode serving as a source for generating a clamping voltage, and a second transistor for clamping the log-compressed voltage if the voltage goes beyond a predetermined clamp voltage. The second transistor has the same form as the first transistor and provides a collector connected to a cathode of the clamp voltage generating diode. The constant current is supplied to the second transistor from a constant current source.
摘要翻译： 对数压缩电路被布置成使得钳位电平与用于放大输入电流的第一晶体管的放大系数无关。 对数压缩电路包括用于放大输入电流的第一晶体管，用于对放大电流进行对数压缩的压缩二极管，用作产生钳位电压的源的钳位电压产生二极管和用于钳位对数压缩电压的第二晶体管 如果电压超过预定的钳位电压。 第二晶体管具有与第一晶体管相同的形式，并提供连接到钳位电压产生二极管的阴极的集电极。 恒定电流从恒定电流源提供给第二晶体管。
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74.发明授权
公开(公告)号：US4843626A
公开(公告)日：1989-06-27
申请号：US884211
申请日：1986-07-10
申请人： Donn R. Werrbach
发明人： Donn R. Werrbach
摘要： A multiband audio frequency signal limiting apparatus suitable for use in a wide range of applications is disclosed. An input signal is divided into discrete frequency bands (any practical number is suitable) which are each passed through a separate limited and subsequently summed to obtain an output signal. The summed output signal is fed into an automatic limit threshold circuit which generates a third signal, the Automatic Limit Threshold (ALT) signal, which modifies a common limiting threshold reference for the bands. This causes the bands to limit at a higher or lower threshold level and the band output levels to increase or decrease in direct proportion to the threshold level of limiting. The ALT signal cause the bands to limit at a lower threshold when the energy content of the various bands would combine toward higher values, which could thus generate a larger than desired output signal level. In this way, the summed output signal will be servoed towards one hundred percent level regardless of the input audio frequency bandwidth (and consequently the individual relative band energy content).
摘要翻译： 公开了一种适用于广泛应用的多频段音频信号限制装置。 输入信号被分成离散频带（任何实际数字是合适的），每个离散频带通过单独的受限并随后相加以获得输出信号。 相加的输出信号被馈送到自动限制阈值电路中，该电路产生第三信号，即自动限制阈值（ALT）信号，其修改频带的公共限制阈值参考。 这导致频带在更高或更低的阈值电平下限制，并且频带输出电平与阈值限制水平成正比地增加或减少。 当各种频带的能量含量将组合到更高的值时，ALT信号使得频带在较低的阈值处被限制，这可以产生大于期望的输出信号电平。 以这种方式，无论输入音频带宽（以及因此各个相对频带能量内容）如何，相加的输出信号将被驱动到百分之百的电平。
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公开(公告)号：US4388540A
公开(公告)日：1983-06-14
申请号：US207326
申请日：1980-11-17
申请人： Peter H. M. Schreurs
发明人： Peter H. M. Schreurs
CPC分类号： H03G3/3042 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0025 , H03D2200/0043 , H03D2200/0084
摘要： A multiplying circuit comprising a pair of transistors including first and second transistors arranged in a long-tailed pair configuration having a collector output and interconnected emitter electrodes coupled to a first current source. A bias voltage adjusting circuit applies equal base bias voltages to the base electrodes of the pair of transistors. The base electrodes are connected to a signal input to provide control of the amplitude of the output signal. The multiplying circuit further comprises a controlled current distribution circuit including a shunting transistor whose collector-emitter path is DC connected in parallel to the pair of transistors. A control circuit supplies a control voltage between the base electrode of the shunting transistor and the base electrodes of the pair of transistors.
摘要翻译： 一种乘法电路，包括一对晶体管，其包括以长尾对配置的第一和第二晶体管，其具有集电极输出和耦合到第一电流源的互连的发射极。 偏置电压调节电路对该对晶体管的基极施加相等的基极偏置电压。 基极连接到信号输入端，以提供对输出信号振幅的控制。 乘法电路还包括受控电流分配电路，其包括其集电极 - 发射极路径与该对晶体管并联连接的分流晶体管。 控制电路在分流晶体管的基极和一对晶体管的基极之间提供控制电压。
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公开(公告)号：US4327431A
公开(公告)日：1982-04-27
申请号：US204827
申请日：1980-11-07
摘要： Under certain conditions a video disc player can be responsive to externally applied interference signals to provide a defect in the display of the information recovered from the disc. Apparatus is provided between the pickup circuits and the normal defect compensation apparatus of the player to detect the presence of the external signals and to activate the normal defect compensation apparatus when the external signals are of a relatively high frequency and above a variable offset or threshold level. The threshold is made to vary as a function of the amplitude of the signal provided at the output of the pickup circuits.
摘要翻译： 在某些条件下，视频光盘播放器可以响应于外部施加的干扰信号，以提供从盘中恢复的信息的显示中的缺陷。 在拾取电路和播放器的正常缺陷补偿装置之间设置检测外部信号的存在的装置，并且当外部信号具有相对高的频率并且高于可变偏移或阈值电平时启动正常的缺陷补偿装置 。 阈值作为在拾取电路的输出处提供的信号的幅度的函数而变化。
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公开(公告)号：US3947806A
公开(公告)日：1976-03-30
申请号：US548722
申请日：1975-02-10
CPC分类号： H03G3/3026 , G01V1/247
摘要： This is a seismic digital recording system for use where the seismic amplifiers are placed near the geophone locations and their outputs transmitted by common cable to the recording truck or recorded on magnetic tape at the geophone location. In such a digital recording system, it is impractical to use a high-speed, high gain-ranging amplifier of 15 or 16 bits range. In our design the gain-ranging amplifier is high-speed but employs fewer bits total range. The extra range is made up in a preamplifier which has a variable range of gain, which can be automatically set, but at slower speed. The invention involves a control system which is responsive to the output of an A/D converter which is connected to the output of the gain-ranging amplifier. This control examines the bit output of the A/D converter throughout the whole record and, depending on whether the most significant bit is a 0 or 1, and whether the less significant bits are 0 or 1, it acts to control the gain of the preamplifier on the suceeding record by increasing the gain, decreasing the gain, or leaving the gain set at its instant value. The gain of the preamplifier can be adjusted by 6-db steps for each succeeding record until it reaches a value for which the operation of the gain-ranging amplifier is optimum.
摘要翻译： 这是一种地震数字记录系统，用于将地震放大器放置在地音检波器位置附近，其输出通过普通电缆传输到记录卡车或记录在地震检波器位置的磁带上。 在这样的数字记录系统中，使用15或16位范围的高速，高增益范围的放大器是不现实的。 在我们的设计中，增益范围放大器是高速的，但总占用范围较少。 额外的范围由具有可变增益范围的前置放大器组成，可以自动设置，但速度较慢。 本发明涉及一种响应于连接到增益测距放大器的输出的A / D转换器的输出的控制系统。 该控制检查整个记录中的A / D转换器的位输出，并且根据最高有效位是0或1，以及较低有效位是否为0或1，它用于控制 通过增加增益，降低增益或将增益设置为其瞬时值，对前一个放大器进行超量记录。 前置放大器的增益可以通过每个后续记录的6-db步长进行调整，直到达到增益范围放大器的工作最佳值。
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公开(公告)号：US3770984A
公开(公告)日：1973-11-06
申请号：US3770984D
申请日：1971-03-03
发明人： CONNOR D , MC DONOUGH R
CPC分类号： H03G3/3005 , H03G11/00
摘要： A signal limiter for reducing and increasing the gain of a circuit with the required speed of response without introducing distortion in the limiter output. The limiter includes a variable gain circuit having an output coupled to a detector in a feedback loop. The detector develops a DC signal which is then coupled back to the gain control device to reduce or increase the gain in accordance with the output signal level. A charging circuit is coupled to a point between the detector and the gain controlling device to hold a high level signal appearing at the output of the detector for a given time interval. Switching means are then provided to discharge the charging circuit after the lapse of a predetermined time interval to allow the gain to return to normal. This assures that the gain of the gain controlling device will not fluctuate in response to every signal waveform peak. Such rapid fluctuations would result in distortion at the output of the limiter. The switching circuit consists of several forms. One of the forms comprises a transistor having a second charging circuit coupled to the emitter thereof. The discharge time of the second charging circuit allows the transistor to be turned on to discharge the main charging circuit and allow the gain of the gain controlling device to return to normal. In a second form, the second charging circuit is coupled to the base of the transistor, and the operation is similar to that described above. In a further embodiment, a switching means of any general configuration may be provided in shunt with the main charging circuit and operated according to a given timing sequence. In another embodiment, a zener diode may be used to discharge the principal charging circuit when the voltage applied to the anode thereof through a second charging circuit decreases to a given level.
摘要翻译： 信号限制器，用于以所需的响应速度减小和增加电路的增益，而不会在限幅器输出中引入失真。 限幅器包括可变增益电路，其具有耦合到反馈回路中的检测器的输出。 检测器产生DC信号，然后将DC信号耦合回增益控制装置，以根据输出信号电平降低或增加增益。 充电电路耦合到检测器和增益控制装置之间的点，以保持出现在检测器的输出处的给定时间间隔的高电平信号。 然后提供开关装置以在经过预定时间间隔之后对充电电路进行放电，以允许增益恢复正常。 这确保增益控制装置的增益不会响应于每个信号波形峰值而波动。 这种快速波动将导致限制器输出的失真。 开关电路由几种形式组成。 一种形式包括具有耦合到其发射极的第二充电电路的晶体管。 第二充电电路的放电时间允许晶体管导通以对主充电电路放电，并允许增益控制装置的增益恢复正常。 在第二种形式中，第二充电电路耦合到晶体管的基极，并且操作类似于上述。 在另一实施例中，可以提供任何一般配置的切换装置，以与主充电电路分流并根据给定的定时顺序进行操作。 在另一个实施例中，当通过第二充电电路施加到其阳极的电压降低到给定电平时，可以使用齐纳二极管来放电主充电电路。
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公开(公告)号：US3737678A
公开(公告)日：1973-06-05
申请号：US3737678D
申请日：1971-01-19
发明人： DOLBY R , ROBINSON D
摘要： Limiters are known utilizing a shunt FET rendered conductive by a smoothed control signal to attenuate a signal. In this invention distortion is reduced by effecting positive feedback of half of the FET output voltage via a control signal smoothing capacitor or by putting the FET across a balanced line on the output side of a phase splitter. Furthermore, by using two or more shunt FETs having different thresholds, better control of the attenuation characteristics over the whole dynamic range is possible.
摘要翻译： 限制器是已知的，利用通过平滑的控制信号导通的并联FET来衰减信号。 在本发明中，通过经由控制信号平滑电容器实现FET输出电压的一半的正反馈，或者通过将FET穿过在分相器的输出侧上的平衡线路来减小失真。 此外，通过使用具有不同阈值的两个或更多个并联FET，可以在整个动态范围内更好地控制衰减特性。
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