公开(公告)号：US09191136B2

公开(公告)日：2015-11-17

申请号：US13600858

申请日：2012-08-31

申请人： Gen Ichimura ,  Hidekazu Kikuchi ,  Yasuhisa Nakajima

发明人： Gen Ichimura ,  Hidekazu Kikuchi ,  Yasuhisa Nakajima

IPC分类号： H04B3/00 ,  H04J3/06 ,  H04L25/02 ,  H04L25/493 ,  H04N21/436 ,  H04N21/4363 ,  H04N21/643 ,  H04L7/00

CPC分类号： H04L25/0276 ,  H04J3/0638 ,  H04J3/0641 ,  H04L7/0016 ,  H04L7/0091 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/493 ,  H04N21/43615 ,  H04N21/43635 ,  H04N21/64322

摘要： A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

摘要翻译： 视频信号和音频信号是从源设备传送到宿设备的TMDS。 通过与TMDS传输线分开提供的预留线路和HPD线路，双向传输以太网™信号，并且还将SPDIF信号从宿设备发送到源设备。 以太网™发送器/接收器电路之间双向传输的以太网™信号由放大器进行差分传输，由放大器接收。 来自SPDIF发送器电路的SPDIF信号是从加法器发送的共模信号，并被加法器接收以提供给SPDIF接收器电路。

公开(公告)号：US20150326384A1

公开(公告)日：2015-11-12

申请号：US14606600

申请日：2015-01-27

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Pei-Si WU

IPC分类号： H04L7/00

CPC分类号： H04L7/0016 ,  H04L7/007 ,  H04L7/0079 ,  H04L7/033

摘要： A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.

公开(公告)号：US09185013B1

公开(公告)日：2015-11-10

申请号：US14314684

申请日：2014-06-25

申请人： Marvell International Ltd.

发明人： Ravi Narasimhan

IPC分类号： H04L27/00 ,  H04L7/00 ,  H04L23/00 ,  H04L12/26 ,  H03L7/091

CPC分类号： H04L43/087 ,  H03L7/091 ,  H04L7/0016 ,  H04L25/0224 ,  H04L25/024 ,  H04L27/2602 ,  H04L27/2656 ,  H04L27/2657 ,  H04L27/2675

摘要： A system including a channel estimator configured to generate an estimate of a communication channel based on a data packet received via the communication channel. A circuit is configured to determine a data rate at which the data packet was received via the communication channel, determine whether the data rate at which the data packet was received via the communication channel is greater than a threshold, and selectively compensate the channel estimate generated by the channel estimator for sampling phase jitter based on the determination of whether the data rate at which the data packet was received via the communication channel is greater than the threshold.

摘要翻译： 一种包括信道估计器的系统，被配置为基于经由通信信道接收的数据分组来生成通信信道的估计。 电路被配置为确定经由通信信道接收数据分组的数据速率，确定经由通信信道接收到数据分组的数据速率是否大于阈值，并且选择性地补偿生成的信道估计 基于通过通信信道接收数据分组的数据速率是否大于阈值的确定来确定采样相位抖动的信道估计器。

公开(公告)号：US20150295704A1

公开(公告)日：2015-10-15

申请号：US14727861

申请日：2015-06-01

申请人： PhasorLab, Inc.

发明人： Joshua C. Park

IPC分类号： H04L7/00 ,  H04L27/00

CPC分类号： H04W56/006 ,  G01S3/18 ,  H04B7/0413 ,  H04L7/0016 ,  H04L25/02 ,  H04L27/0014 ,  H04L27/364 ,  H04L2027/003 ,  H04L2027/0046 ,  H04L2027/0053 ,  H04L2027/0067 ,  H04W56/0035 ,  H04W64/006

摘要： A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase.

公开(公告)号：US20150295702A1

公开(公告)日：2015-10-15

申请号：US14647324

申请日：2013-08-15

申请人： NEC Corporation

发明人： Takatoshi OGAWA

IPC分类号： H04L7/00

CPC分类号： H04L7/0016 ,  H04J3/0638 ,  H04J3/0644 ,  H04J3/0647 ,  H04J3/0658 ,  H04J3/0667 ,  H04W56/0015 ,  H04W56/0035

摘要： A synchronization apparatus capable of reducing the effect of the fluctuations in synchronization signals that are caused when the synchronization signals are received through a network are provided. A synchronization apparatus (20) according to the present invention receives a synchronization signal transmitted from a synchronization signal source (10) through a network. The synchronization apparatus (20) includes a frequency synchronization unit (21) that performs frequency synchronization based on a received synchronization signal, and outputs a frequency synchronization signal, a phase synchronization unit (23) that performs phase synchronization based on a synchronization signal transmitted from the synchronization signal source (10) through a network, and outputs a phase synchronization signal, and a phase synchronization control unit (22) that generates an offset value by using a phase difference between the frequency synchronization signal and the phase synchronization signal, and corrects a phase of the frequency synchronization signal by using the offset value.

摘要翻译： 提供能够减少通过网络接收同步信号时产生的同步信号的波动的影响的同步装置。 根据本发明的同步装置（20）通过网络接收从同步信号源（10）发送的同步信号。 同步装置（20）包括：频率同步单元（21），其基于接收到的同步信号进行频率同步，并输出频率同步信号;相位同步单元（23），其基于从 通过网络同步信号源（10），并输出相位同步信号;以及相位同步控制单元（22），通过使用频率同步信号和相位同步信号之间的相位差产生偏移值，并且校正 通过使用偏移值的频率同步信号的相位。

公开(公告)号：US20150256325A1

公开(公告)日：2015-09-10

申请号：US14718019

申请日：2015-05-20

申请人： Rambus Inc.

发明人： Craig E. Hampel ,  Frederick A. Ware ,  Richard E. Perego

IPC分类号： H04L7/00

CPC分类号： H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

摘要翻译： 提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于 而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

公开(公告)号：US20150195081A1

公开(公告)日：2015-07-09

申请号：US14417447

申请日：2013-08-27

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Wataru Matsumoto ,  Toshiaki Akino ,  Yoshikuni Miyata ,  Kenya Sugihara ,  Takashi Sugihara ,  Takafumi Fujimori

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0016 ,  H03M13/1105 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/45 ,  H03M13/63 ,  H04B1/76 ,  H04L1/005 ,  H04L1/0057 ,  H04L7/0079 ,  H04L7/033

摘要： A transmitter for transmitting a transmission signal subjected to modulation after error correction coding and a receiver including a phase compensation unit for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data.

摘要翻译： 一种发送器，用于发送在纠错编码之后进行调制的发送信号;以及接收机，包括用于接收发送信号的相位补偿单元，并进行解调，同时保持同步;以及纠错解码单元，对接收到的数据进行解码处理， 已经进行了解调。 发射机发送由多个导频序列形成的信号作为发送信号的一部分，并且接收机具有用于通过使用多个导频序列来估计相位补偿单元的相位滑移的相位滑移估计处理功能，并且 由纠错解码单元估计相位差分量，从而校正接收数据的相位。

公开(公告)号：US09065457B2

公开(公告)日：2015-06-23

申请号：US13870742

申请日：2013-04-25

申请人： Skyworks Solutions, Inc.

发明人： Ardeshir Namdar-Mehdiabadi ,  Darren Roger Frenette ,  John William Mitchell Rogers

IPC分类号： H03D3/24 ,  H03L7/197 ,  H04L7/00 ,  H03L7/089

CPC分类号： H03L7/1974 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197 ,  H03L7/1976 ,  H03L7/1978 ,  H04L7/0016 ,  H04L7/0045 ,  H04W56/0035 ,  H04W88/02

摘要： Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

摘要翻译： 公开了用于减少或消除频率合成器中的参考杂散的电路和方法。 在一些实现中，诸如频率合成器的Frac-N PLL的锁相环（PLL）可以包括被配置为接收参考信号和反馈信号的相位频率检测器（PFD）。 PFD可以被配置为产生表示参考信号和反馈信号之间的相位差的第一信号。 PLL还可以包括被配置为基于第一信号产生补偿信号的补偿电路。 PLL还可以包括被配置为基于补偿信号产生输出信号的压控振荡器（VCO）。 补偿信号可以包括用于基本上消除与PLL相关联的一个或多个参考杂波的至少一个特征。

公开(公告)号：US09042504B2

公开(公告)日：2015-05-26

申请号：US14201778

申请日：2014-03-07

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC分类号： H04L7/00 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C7/04 ,  H04L7/033

CPC分类号： H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

摘要翻译： 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

公开(公告)号：US09036729B2

公开(公告)日：2015-05-19

申请号：US13873003

申请日：2013-04-29

申请人： LSI Corporation

发明人： Hiep Pham ,  Chaitanya Palusa ,  Tomasz Prokop ,  Adam Healey

IPC分类号： H04L7/00 ,  H04L27/12 ,  H03L7/06 ,  H03L7/08 ,  H04L7/027 ,  H03L7/099

CPC分类号： H04L27/122 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0998 ,  H04L7/0012 ,  H04L7/0016 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/027

摘要： A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.

摘要翻译： 中继器包括时钟和数据恢复元件以及从数据流提取嵌入式时钟频率的相位内插器。 相位插值器确定频率偏移，并将相位内插器码的偏移发送到滤波器和缩放器。 滤波的，缩放的相位内插器码用于产生用于重传的参考时钟频率。