Abstract:
Timing oscillators as well as related methods and devices are described. A timing oscillator may include a mechanical resonating structure with major elements and minor elements coupled to the major element. The timing oscillator can generate stable signals with low phase noise at very high frequencies which allows a timing oscillator to be used effectively in a number of devices including computers and mobile phones for time and data synchronization purposes. The signal generated by the timing oscillator can be tuned using a driver circuit and a compensation circuit.
Abstract:
The fundamental breakthrough in green technology are the Varactor Free Amplitude Controlled Oscillator VFACO and the planar EMI-Free Planar Inductor. The VFACO makes the fine tune for oscillation frequency. It has the frequency compensation over temperature. It doesn't have the VCO self-modulation-induced phase noise. It is phase-noiseless. It is high-Q and high stability. It increases the communication capacity. The EMI-Free Planar Inductor is the backbone of the platform of green technology. The platform of green technology contains the Xtaless ClockChip, Inductorless PMU & PA and ESDS-PCB to provide the green technology for green chip design. Especially for the 4th generation wireless communication, the Inductorless PMU & PA are the most important green technology. The Xtaless ClockChip adopts the most advanced self-compensation Amplitude controller. The ESDS-PCB has the minimum Via assignment algorithm to make the optimum pin assignment for the platform of green technology. The self-compensation Amplitude controller is so powerful that the Xtaless ClockChip is trimless and/or trimfree Xtaless ClockChip. It is plastic-packageable and IP-able Xtaless ClockChip that it is the only market-ready-product Xtaless ClockChip.
Abstract:
Apparatus and methods for stabilizing reference oscillators are described. According to some embodiments, the reference oscillator of a device may be stabilized by synchronizing the reference oscillator to an external signal received by the device. The device may be a navigation device in some embodiments, and the external signal may represent or be synchronized to an atomic clock signal or other signal exhibiting sufficient stability.
Abstract:
A circuit comprises a frequency divider configured to receive an oscillating signal generated by an oscillator and to divide the oscillating signal into a clock signal, wherein the division ratio of the frequency divider is set to a value equal to one of: the integer part of the resonant frequency of the oscillator and the integer part of the resonant frequency of the oscillator plus 1.
Abstract:
Disclosed herein is a current source, including: a current control oscillator configured to output an oscillation signal of a frequency dependent on an input current; a comparator configured to compare the oscillation signal with a reference signal; a charge pump configured to output a current dependent on a comparison result by the comparator; a low-pass filter configured to include a smoothing capacitor charged and discharged by an output current of the charge pump; a loop converter configured to be connected to the smoothing capacitor and generate a current dependent on a voltage generated by the smoothing capacitor to supply the current as the input current to the current control oscillator; and an output converter configured to be connected to the low-pass filter and generate a current dependent on a voltage generated in the low-pass filter to output the current as an output current.
Abstract:
In one exemplary implementation, an electronic apparatus includes: a reference clock source, for generating a reference clock; a global navigation satellite system (GNSS) receiver for receiving satellites signals and the reference clock, comprising: a monitoring circuit, for monitoring a status of the GNSS receiver to generate a monitoring result; and a compensating circuit, coupled to the reference clock source and the monitoring circuit, for compensating the reference clock according to the monitoring result.
Abstract:
A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods may include generating incremented counter values at a counter responsive to edges of the second clock signal. For at least two of the plurality of calibration periods, an initial incremented counter value from the counter may be stored in memory at an initial edge of the first clock signal for the respective calibration period, a final incremented counter value may be stored in memory at a final edge of the clock signal for the respective calibration period, and the at least two of the plurality of calibration periods may be overlapping with different initial and final edges of the first clock signal. For each of the plurality of calibration periods, a number of edges of the second clock signal occurring during the respective calibration period may be determined using the initial and final incremented counter values stored in memory. A relationship between the first and second clock signals may be determined using a sum of a number of edges of the second clock signal occurring during each of the plurality of calibration periods and using a sum of a number of first clock signal cycles occurring during each of the plurality of calibration periods.
Abstract:
An oscillator that increases the accuracy of an output frequency, without using a charge pump, has an oscillation circuit, first and second voltage supply circuits, and a calibration value generation circuit. The first voltage supply circuit includes a resistor and a capacitor, the resistance and capacitance of which are determined so that a first voltage reaches a reference voltage within a reference time. The second voltage supply circuit includes first and second switching means, which perform switching when receiving pulse signals corresponding to the frequency of the oscillation circuit to raise the second voltage. A calibration value generation circuit provides the oscillation circuit with a calibration value that lowers the frequency when the second voltage reaches the reference voltage before the first voltage and raises the frequency when the second voltage reaches the reference voltage after the first voltage.
Abstract:
An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, VBN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, VBP, referenced to a positive power supply (VDD). The VBP and VBN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into VDD and GND.
Abstract:
Method and systems are provided for adjusting real-time clocks to compensate for frequency offset, temperature effects, and/or aging effects.