公开(公告)号：US07127110B1

公开(公告)日：2006-10-24

申请号：US09530136

申请日：1998-10-03

Applicant: Yuri Hasegawa ,  Shunichi Sekiguchi ,  Shinichi Kuroda ,  Kohtaro Asai ,  Hirofumi Nishikawa ,  Yoshimi Isu

Inventor： Yuri Hasegawa ,  Shunichi Sekiguchi ,  Shinichi Kuroda ,  Kohtaro Asai ,  Hirofumi Nishikawa ,  Yoshimi Isu

IPC: G06K9/36

CPC classification number: G06F9/45525 ,  H04N19/00 ,  H04N19/107 ,  H04N19/132 ,  H04N19/172 ,  H04N19/176 ,  H04N19/20 ,  H04N19/21 ,  H04N19/29 ,  H04N19/31 ,  H04N19/39 ,  H04N19/46 ,  H04N19/50 ,  H04N19/587 ,  H04N19/61 ,  H04N19/70 ,  H04N21/234318 ,  H04N21/23614 ,  H04N21/4307 ,  H04N21/4348 ,  H04N21/440281 ,  H04N21/6332 ,  H04N21/654 ,  H04N21/6547

Abstract: A coded bit stream generated on a coding side consists of a VO header, a VOL header, a GOV header, a VOP header and VOP data, and the VOL header multiplexes an object intra-coded indicator signal indicating whether all the VOP data contained in a VOL or GOV are intra coded or not. This enables a decoding side to recognize whether all the VOP data contained in the VOL or GOV in the coded bit stream are intra coded or not by only analyzing the object intra-coded indicator signal. This can facilitate such processings as frame skip control or random access of the VOPs.

Abstract translation: 在编码侧生成的编码比特流由VO头，VOL头，GOV头，VOP头，VOP数据构成，VOL头多路复用指示是否包含的所有VOP数据的对象帧内编码指示信号 VOL或GOV是内部编码的。 这使得解码侧能够通过仅分析对象帧内编码指示符信号来识别编码比特流中包含在VOL或GOV中的所有VOP数据是否被帧内编码。 这可以促进诸如帧跳过控制或VOP的随机访问的处理。

公开(公告)号：US20050149704A1

公开(公告)日：2005-07-07

申请号：US10681404

申请日：2003-10-08

Applicant: Luther Johnson

Inventor： Luther Johnson

IPC: G06F9/00 ,  G06F9/318 ,  G06F9/38 ,  G06F9/42 ,  G06F9/45

CPC classification number: G06F9/30181 ,  G06F8/52 ,  G06F9/3808 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3897 ,  G06F9/4486 ,  G06F9/45525

Abstract: The invention uses a standard processor to execute an application program. As the instructions of the application program are executed in sequence, a program counter is incremented to contain an address indicator of the next instruction to be executed. The address indicator from the program counter is also fed to a function lookup unit where it is matched to the contents of a tag field. If there is no match, control returns to the processor which continues its normal sequence of operations and performs the function. If there is a match, function indicator identifiers from the function lookup table are fed to a reconfigurable combinational array which has logic functions. The function indicator identifiers select the logic function to be performed. The result of the performed function including the new program counter is then fed back to the processor. The processor then continues its normal operations.

Abstract translation: 本发明使用标准处理器来执行应用程序。 随着应用程序的指令按顺序执行，程序计数器递增，以包含要执行的下一个指令的地址指示符。 来自程序计数器的地址指示符也被馈送到与标签字段的内容匹配的功能查找单元。 如果没有匹配，则控制返回到处理器，继续其正常的操作顺序并执行该功能。 如果存在匹配，则来自功能查找表的功能指示符标识符被馈送到具有逻辑功能的可重组组合阵列。 功能指示标识符选择要执行的逻辑功能。 包括新的程序计数器的执行功能的结果然后被反馈给处理器。 然后处理器继续其正常操作。

公开(公告)号：US20040117779A1

公开(公告)日：2004-06-17

申请号：US10727202

申请日：2003-12-03

Applicant: BEA SYSTEMS, INC.

Inventor： Marcus Lagergren

IPC: G06F009/45

CPC classification number: G06F9/45525 ,  G06F8/4434

Abstract: A system and method for iterative code optimization using adaptive or dynamic size metrics, for use with run-time software systems and virtual machines. The dynamic size metric may be calculated both for a set of predetermined factors (together with associated weights), and also for a set of variable factors determined during the runtime code introspection process. The predetermined factors, and their associated weights, may be varied to reflect the overall performance of the code in each optimization instance. In one embodiment a method is provided for performing adaptive optimization of application code within a virtual machine environment, the method comprising the steps of: gathering information about an application code and optimization parameters during run-time, passing said information via a feedback mechanism to an optimizer, calculating a dynamic size metric for the current application code using said optimization parameters, and optimizing the application code based on the dynamic size metric.

Abstract translation: 一种用于使用自适应或动态大小度量进行迭代代码优化的系统和方法，用于运行时软件系统和虚拟机。 可以针对一组预定因素（连同相关联的权重）以及对于在运行时代码反省过程期间确定的一组可变因子来计算动态尺寸度量。 可以改变预定因子及其相关权重以反映每个优化实例中的代码的整体性能。 在一个实施例中，提供一种用于在虚拟机环境内执行应用代码的自适应优化的方法，所述方法包括以下步骤：在运行时间期间收集关于应用代码和优化参数的信息，将所述信息经由反馈机制传递到 优化器，使用所述优化参数计算当前应用代码的动态尺寸度量，以及基于动态尺寸度量优化应用代码。

公开(公告)号：US06631514B1

公开(公告)日：2003-10-07

申请号：US09003572

申请日：1998-01-06

Applicant: Bich-Cau Le

Inventor： Bich-Cau Le

IPC: G06F945

CPC classification number: G06F9/30174 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/45525

Abstract: The inventive emulator dynamically translates instructions in code written for a first architecture into code for a second architecture. The emulator designates various checkpoints in the original code, and speculatively reorders the placement of the translated code instructions according to optimization procedures. If during the execution of the reordered code, a trap should occur, then the emulator resets the original code to the most recent checkpoint and begins executing the original code sequentially in a line-by-line manner until the section is completed or branched out of. The original code is reset by changing the program counter to the checkpoint, and reversing the effects of each instruction which has been executed subsequent to the checkpoint. Thus, any native instructions which correspond to original instructions which occur sequentially prior to the checkpoint have been executed, and any native instructions which correspond to original instructions which occur sequentially subsequent to the checkpoint have not been executed.

Abstract translation: 本发明的仿真器将针对第一架构编写的代码中的指令动态地转换为用于第二架构的代码。 仿真器指定原始代码中的各种检查点，并根据优化过程推测重新排序翻译的代码指令的位置。 如果在执行重新排序的代码期间，应该发生陷阱，然后仿真器将原始代码重置到最近的检查点，并以逐行方式顺序执行原始代码，直到该段完成或分支为止 。 通过将程序计数器更改为检查点来重置原始代码，并反转在检查点之后执行的每条指令的效果。 因此，对应于在检查点之前顺序发生的原始指令的任何本地指令已被执行，并且与检查点之后顺序发生的对应于原始指令的任何本地指令尚未被执行。

公开(公告)号：US11875168B2

公开(公告)日：2024-01-16

申请号：US17176824

申请日：2021-02-16

Applicant: Oracle International Corporation

Inventor： Maurizio Cimadamore ,  James Malcolm Laskey ,  Jorn Bender Vernee ,  Vladimir Vitalyevich Ivanov

IPC: G06F9/455 ,  G06F9/448

CPC classification number: G06F9/45525 ,  G06F9/449 ,  G06F9/45558 ,  G06F9/4488 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: Techniques for reducing overhead in native function calls are disclosed. The system may receive a method invocation instruction for invoking a particular method. The method invocation instruction includes a function descriptor, a method type, and an application binary interface (ABI) descriptor. The function descriptor includes a memory layout corresponding to any data returned by the function and memory layouts corresponding to each argument for the particular method. The system can select an ABI for processing the particular method based on the received ABI descriptor. The system can further associate each argument with a corresponding particular physical register into which the argument is to be loaded. The particular register is selected based on at least the selected ABI and the function descriptor. The system can cause a virtual machine to move each argument into the corresponding associated physical register.

公开(公告)号：US20190155580A1

公开(公告)日：2019-05-23

申请号：US16257610

申请日：2019-01-25

Applicant: Citrix Systems, Inc.

Inventor： Dan Gulkis

IPC: G06F8/30 ,  G06F9/455 ,  G06F9/445

CPC classification number: G06F8/315 ,  G06F9/445 ,  G06F9/44521 ,  G06F9/45504 ,  G06F9/45525

Abstract: Methods, systems, and computer-readable media for providing a virtualization layer for mobile applications are presented. A computing device may parse code of an application to identify a first set of one or more classes in the application. The computing device may transmit code usable by the first set of one or more classes to a module accessible to the application and create a second set of one or more classes in the application to replace the first set of one or more classes, wherein the second set of one or more classes does not inherit from the first set of one or more classes in an object hierarchy. In some embodiments, the second set of one or more classes provides at least one different function from the first set of one or more classes. The computing device may execute the application comprising the second set of one or more classes.

公开(公告)号：US20190079811A1

公开(公告)日：2019-03-14

申请号：US15704156

申请日：2017-09-14

Applicant: Oracle International Corporation

Inventor： Alexander R. Buckley ,  Alan Bateman

IPC: G06F9/54 ,  G06F9/455

CPC classification number: G06F9/542 ,  G06F9/45504 ,  G06F9/45525 ,  G06F9/45533 ,  G06F2209/463

Abstract: Techniques for renaming a module in a module system are disclosed. It is determined that a first module is declared with a corresponding first module name. It is determined that the first module is associated with a second module name. Responsive to determining that the first module is associated with the second module name: a second module declared with the second module name is synthesized, and a dependency of the second module, with the second module name, is declared on the first module with the first module name.

公开(公告)号：US20180349159A1

公开(公告)日：2018-12-06

申请号：US15608165

申请日：2017-05-30

Applicant: PayPal, Inc.

Inventor： Shlomi Boutnaru

IPC: G06F9/455 ,  G06F9/445 ,  H04L29/06 ,  G06F9/45

CPC classification number: G06F9/5027 ,  G06F8/443 ,  G06F9/445 ,  G06F9/45516 ,  G06F9/45525 ,  G06F9/50 ,  G06F9/5044 ,  G06F9/5077 ,  G06F11/30 ,  G06F11/3466 ,  G06N3/126 ,  H04L67/02 ,  H04L67/04 ,  H04L67/1004 ,  H04L67/101 ,  H04L67/1025 ,  H04L67/42

Abstract: A system and method for optimizing runtime environments for applications by running the applications in a plurality of runtime environments and iteratively selecting and creating new runtime environments based on a fitness score determined for the plurality of runtime environments.

公开(公告)号：US09977663B2

公开(公告)日：2018-05-22

申请号：US15200053

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Gilles A. Pokam

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/447 ,  G06F8/452 ,  G06F9/45525

Abstract: Technologies for optimizing sparse matrix code include a target computing device having a processor and a field-programmable gate array (FPGA). A compiler identifies a performance-critical loop in a sparse matrix source code and generates optimized executable code, including processor code and FPGA code. The target computing device executes the optimized executable code, using the processor for the processor code and the FPGA for the FPGA code. The processor executes a first iteration of the loop, generates reusable optimization data in response to executing the first iteration, and stores the reusable optimization data in a shared memory. The FPGA accesses the optimization data in the shared memory, executes additional iterations of the loop, and optimizes the additional iterations of the loop based on the optimization data. The optimization data may include, for example, loop-invariant data, reordered data, or alternate data storage representations. Other embodiments are described and claimed.

公开(公告)号：US20180060048A1

公开(公告)日：2018-03-01

申请号：US15407186

申请日：2017-01-16

Applicant: Google Inc.

Inventor： Andreas Gampe ,  Nicolas Geoffray ,  Mingyao Yang

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/42 ,  G06F9/449 ,  G06F9/4552 ,  G06F9/45525

Abstract: Apparatus and methods related to compiling software are provided. A computing device can receive software having software-associated instructions for compilation into machine-language instructions. The computing device can perform a class hierarchy analysis to determine a class hierarchy for the software. The computing device can determine whether a particular method call is to be checked for execution as a virtual method call based on the class hierarchy. The computing device can, after determining that the particular method call is to be checked, determine particular machine-language instructions that can include: guarding machine-language instructions for checking a runtime-modifiable deoptimization indicator to determine whether the particular method call is to be executed as a virtual method call, and method-call machine-language instructions for the particular method call. The computing device can provide the particular machine-language instructions to a runtime system.