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71.发明申请公开(公告)号：US20180025100A1
公开(公告)日：2018-01-25
申请号：US15214354
申请日：2016-07-19
申请人： Altera Corporation
发明人： Sergey Gribok
CPC分类号： G06F17/505 , G06F7/52 , G06F7/535 , G06F8/443 , G06F17/5054 , G06F2207/5356 , G06F2217/84
摘要： A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.
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公开(公告)号：US09448570B2
公开(公告)日：2016-09-20
申请号：US14487198
申请日：2014-09-16
发明人： Shinya Naoi , Yasuhiro Noro , Yasuyuki Miyazaki , Takahiro Shimoo , Toshiaki Asano , Hideyuki Miyaji , Shinji Yurino , Yuji Watanabe
摘要： According to an embodiment, a voltage fluctuation suppressing apparatus is provided with a power storage device connected to an electric power system, a basic control unit to control an output of the power storage device, a voltage detector to measure a voltage of a connection point to the electric power system, and an output control unit to divide a control amount to be outputted to the basic control unit into a reactive power command value and an active power command value and to output them. The output control unit is provided with a reactive power upper limit value calculation unit, a reactive power calculation/output unit, and an active power calculation/output unit.
摘要翻译： 根据实施例，电压波动抑制装置具有连接到电力系统的蓄电装置，用于控制蓄电装置的输出的基本控制单元，电压检测器，用于测量连接点 电力系统和输出控制单元，将输出到基本控制单元的控制量分成无功功率指令值和有功功率指令值，并输出。 输出控制单元设置有无功功率上限值计算单元，无功功率计算/输出单元和有功功率计算/输出单元。
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公开(公告)号：US20160246572A1
公开(公告)日：2016-08-25
申请号：US15049030
申请日：2016-02-20
发明人： Zhengya ZHANG , Chia-Hsiang CHEN
CPC分类号： G06F7/52 , G06F5/01 , G06F7/535 , G06F2205/00 , G06F2207/5356
摘要： A reciprocal unit for computing an estimated reciprocal of a number represented by a bit string. The unit comprises a first lookup table configured to receive one or more of the bits in the bit string and to output an initial estimate of the reciprocal of the number. The unit further comprises a second lookup table configured to receive one or more of the bits in the bit string and to output the square of the initial estimate of the reciprocal of the number. The unit still further comprises a multiplier circuit configured to multiply the square of the initial estimate by the number, and an adder-subtractor circuit for subtracting the product of the multiplication from a scaled value of the initial estimate to determine a final estimate of the reciprocal of the number.
摘要翻译： 用于计算由位串表示的数字的估计倒数的互逆单元。 该单元包括第一查找表，其被配置为接收位串中的一个或多个比特，并输出该数的倒数的初始估计。 该单元还包括第二查找表，其被配置为接收位串中的一个或多个比特，并输出该数的倒数的初始估计的平方。 该单元还包括乘法器电路，其被配置为将初始估计的平方乘以该数，以及加法器 - 减法器电路，用于从初始估计的缩放值中减去乘法乘积以确定倒数的最终估计 的数量。
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公开(公告)号：US09395953B2
公开(公告)日：2016-07-19
申请号：US14300436
申请日：2014-06-10
申请人： Altera Corporation
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译： 可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。 在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。 在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。
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75.发明申请DATA STORAGE METHOD, TERNARY INNER PRODUCT OPERATION CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND TERNARY INNER PRODUCT ARITHMETIC PROCESSING PROGRAM 审中-公开数据存储方法，内部产品操作电路，包括其的半导体器件和三次内部产品算术处理程序公开(公告)号：US20160054979A1
公开(公告)日：2016-02-25
申请号：US14797104
申请日：2015-07-11
发明人： Shunsuke OKUMURA
IPC分类号： G06F7/52
摘要： A data storage method includes storing a plurality of pieces of 2-bit wide ternary data in one word, each of the plurality of pieces of 2-bit wide ternary data indicating +1 when a first bit indicates a first value, indicating −1 when a second bit indicates the first value, and indicating 0 when both the first bit and the second bit indicate a second value.
摘要翻译： 一种数据存储方法包括将一段2位宽的三进制数据存储在一个字中，当第一位指示第一个值时，多个2位宽的三进制数据中的每一个表示+1，表示-1 第二位指示第一值，并且当第一位和第二位都指示第二值时指示0。
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公开(公告)号：US20150220306A1
公开(公告)日：2015-08-06
申请号：US14602573
申请日：2015-01-22
申请人： FUJITSU LIMITED
发明人： Izuho Minaki , Masaki Nishigaki , Naohiro Itou , Kokichi Sugiyama , Tatsuya Yamamoto , Asami Hasegawa
摘要： A computer-readable recording medium having stored therein a calculation program causing a computer to execute a process includes: dividing each of subtracted value data and subtraction value data into a plurality pieces of data in a byte; comparing sizes of each of the divided pieces of subtracted value data and each of the divided pieces of subtraction value data, which have a corresponding digit position; adding carry-down value data that is obtained from digit information of each of the divided pieces of subtracted value data, to the divided corresponding piece of subtracted value data, in accordance with a comparison result; and subtracting each of the divided pieces of subtraction value data, from the divided piece of subtracted value data, to which the carry-down value data is add, and which has the corresponding digit position.
摘要翻译： 一种计算机可读记录介质，其中存储有使计算机执行处理的计算程序，包括：将每个减法值数据和减法值数据分成多个字节数据; 比较每个所分割的相减数据数据的大小和分别的减法值数据的每一个具有对应的数字位置; 根据比较结果，将从每个被分割的相减数据数据的数字信息获得的进位值数据添加到分割的对应的减法值数据; 并从所分割的减法值数据中减去每个所分割的减法值数据，所述减法值数据被添加到其中，并且具有对应的数字位置。
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公开(公告)号：US08788562B2
公开(公告)日：2014-07-22
申请号：US13042700
申请日：2011-03-08
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译： 可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。 在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。 在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。
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公开(公告)号：US20140079159A1
公开(公告)日：2014-03-20
申请号：US14088304
申请日：2013-11-22
发明人： James A. Johnson
IPC分类号： H04B1/16
摘要： A phasor-based pulse detection system includes a first multiplier stage configured to apply a first delayed conjugate multiplication operation to an input signal. The system can also include a second multiplier stage coupled to the first multiplier stage and configured to apply a second delayed conjugate multiplication operation to an output of the first multiplier stage, and an absolute value unit coupled to the second multiplier stage and configured to perform an absolute value operation on an output of the second multiplier stage. The system can further include video filter stage coupled to the absolute value unit and configured to perform a video filtering operation on an output of the absolute value unit. The system can also include a hysteresis detector coupled to the video filter stage, the hysteresis detector configured for detecting a signal in a filtered video signal received from the video filter stage, the detecting including determining a signal start when the filtered video signal exceeds a predetermined detection threshold for a first predetermined number of consecutive samples, and determining a signal end when the filtered video signal falls below a predetermined rejection threshold for a second predetermined number of consecutive samples.
摘要翻译： 基于相量的脉冲检测系统包括：第一乘法器级，被配置为对输入信号施加第一延迟共轭乘法运算。 该系统还可以包括耦合到第一乘法器级并被配置为对第一乘法器级的输出施加第二延迟共轭乘法运算的第二乘法器级和耦合到第二乘法器级的绝对值单元，并且被配置为执行 对第二乘法器级的输出进行绝对值运算。 该系统还可以包括耦合到绝对值单元并被配置为对绝对值单元的输出执行视频滤波操作的视频滤波器级。 该系统还可以包括耦合到视频滤波器级的滞后检测器，滞后检测器被配置用于检测从视频滤波器级接收的经过滤波的视频信号中的信号，该检测包括当滤波的视频信号超过预定值时确定信号开始 第一预定数量的连续样本的检测阈值，以及当滤波的视频信号在第二预定数量的连续样本下降到低于预定拒绝阈值时确定信号结束。
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公开(公告)号：US20140006755A1
公开(公告)日：2014-01-02
申请号：US13538523
申请日：2012-06-29
申请人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
发明人： Shay Gueron , Vlad Krasnov , Robert Valentine , Zeev Sperber , Amit Gradstein , Simon Rubanovich
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F7/52 , G06F9/30018 , G06F9/30036
摘要： An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
摘要翻译： 描述了具有指令执行流水线的装置，其具有支持向量乘法加法指令的向量功能单元。 向量乘以相乘指令乘以两个向量的各个K位元素，并将其各自产物的一部分与X位累加器中的另一个相应输入操作数进行累加，其中X大于K.
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公开(公告)号：US20130346463A1
公开(公告)日：2013-12-26
申请号：US13529619
申请日：2012-06-21
申请人： Scott A. Hilker , George Q. Phan
发明人： Scott A. Hilker , George Q. Phan
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/483 , G06F7/4876 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F2207/382 , G06F2207/3884
摘要： The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.
摘要翻译： 所公开的实施例涉及用于准确，有效和快速地执行乘法指令的装置。 所公开的实施例可以提供具有优化布局的乘法器模块，其可以在乘法运算期间有助于加速结果的计算，从而可以减少周期延迟，从而可以降低功耗。
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