公开(公告)号：US08765562B2

公开(公告)日：2014-07-01

申请号：US13613858

申请日：2012-09-13

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC: H01L21/331 ,  H01L21/8224 ,  H01L29/15 ,  H01L29/739

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/7395

Abstract: A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate.

Abstract translation: 具有p型的集电极层形成在具有n型的碳化硅衬底上。 在集电体层的顶面侧形成有n型漂移层。 设置在漂移层上并具有p型的体区，并且形成设置在身体区域上以通过身体区域与移动层分离并具有n型的发射极区域。 通过去除碳化硅衬底来暴露集电极层的底表面侧。

公开(公告)号：US08686434B2

公开(公告)日：2014-04-01

申请号：US13063083

申请日：2009-02-03

Applicant: Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Masato Tsumori

Inventor： Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Masato Tsumori

IPC: H01L29/06

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/94

Abstract: There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm−3.

Abstract translation: 提供了具有优异的电特性如沟道迁移率的碳化硅半导体器件及其制造方法。 半导体器件包括相对于{0001}的表面取向具有大于或等于50°且小于或等于65°的偏角度的碳化硅制成的衬底，用作 半导体层和用作绝缘膜的氧化膜。 p型层形成在基板上，由碳化硅制成。 氧化膜形成为与p型层的表面接触。 半导体层与绝缘膜（沟道区域和氧化物膜之间的界面）的界面的10nm以内的区域的氮原子的浓度的最大值为1×1021cm-3以上。

公开(公告)号：USD692843S1

公开(公告)日：2013-11-05

申请号：US29431909

申请日：2012-09-12

Applicant: Takeyoshi Masuda

Designer： Takeyoshi Masuda

公开(公告)号：US08536583B2

公开(公告)日：2013-09-17

申请号：US13063298

申请日：2010-03-23

Applicant: Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

Inventor： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

IPC: H01L29/15 ,  H01L31/0312

CPC classification number: H01L29/7802 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/94

Abstract: A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.

Abstract translation: MOSFET包括：碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 MOSFET的子阈值斜率不超过0.4 V /十年。

公开(公告)号：US20130112996A1

公开(公告)日：2013-05-09

申请号：US13805279

申请日：2011-07-14

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L29/16 ,  H01L21/04

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8613 ,  Y10S438/931

Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

Abstract translation: 提供了具有稳定特性的高质量半导体器件和制造这种半导体器件的方法。 半导体器件包括具有主表面的基底和碳化硅层。 碳化硅层形成在基板的主表面上。 碳化硅层包括作为相对于主表面倾斜的端面的侧表面。 在碳化硅层为六方晶型的情况下，侧表面基本上包括{03-3-8}面和{01-1-4}面之一，并且基本上包括{100}面 碳化硅层为立方晶型的情况。

公开(公告)号：US20130045592A1

公开(公告)日：2013-02-21

申请号：US13695775

申请日：2011-11-04

Applicant: Tomihito Miyazaki ,  Hiromu Shiomi ,  Hideto Tamaso ,  Takeyoshi Masuda

Inventor： Tomihito Miyazaki ,  Hiromu Shiomi ,  Hideto Tamaso ,  Takeyoshi Masuda

IPC: H01L21/265 ,  C23C16/40

CPC classification number: H01L29/7802 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/0209 ,  H01L21/02236 ,  H01L21/049 ,  H01L21/28238 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method for manufacturing a SiC semiconductor device includes: a step of forming an oxide film on a surface of a SiC substrate; and a step of removing the oxide film. In the step of forming the oxide film, ozone gas is used. In the step of removing the oxide film, it is preferable to use halogen plasma or hydrogen plasma. In this way, problems associated with a chemical solution can be reduced while obtaining a method and device for manufacturing a SiC semiconductor device, by each of which a cleaning effect can be improved.

Abstract translation: 一种制造SiC半导体器件的方法包括：在SiC衬底的表面上形成氧化膜的步骤; 以及去除氧化膜的步骤。 在形成氧化膜的步骤中，使用臭氧气体。 在除去氧化膜的步骤中，优选使用卤素等离子体或氢等离子体。 以这种方式，可以减少与化学溶液相关的问题，同时获得用于制造SiC半导体器件的方法和装置，通过这些方法和装置可以提高清洗效果。

公开(公告)号：US20120309195A1

公开(公告)日：2012-12-06

申请号：US13579815

申请日：2011-07-29

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L21/302

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8613 ,  Y10S438/931

Abstract: A method for manufacturing a high-quality semiconductor device having stable characteristics is provided. The method for manufacturing the semiconductor device includes the steps of: preparing a silicon carbide layer having a main surface; forming a trench in the main surface by removing a portion of the silicon carbide layer; and removing a portion of a side wall of the trench by thermal etching.

Abstract translation: 提供了一种制造具有稳定特性的高质量半导体器件的方法。 制造半导体器件的方法包括以下步骤：制备具有主表面的碳化硅层; 通过去除一部分碳化硅层在主表面上形成沟槽; 以及通过热蚀刻去除沟槽的侧壁的一部分。

公开(公告)号：US20120309174A1

公开(公告)日：2012-12-06

申请号：US13577836

申请日：2011-12-07

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda

IPC: H01L21/20

CPC classification number: H01L29/7802 ,  H01L21/0475 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method of manufacturing a MOSFET includes the steps of preparing a silicon carbide substrate, forming an active layer on the silicon carbide substrate, forming a gate oxide film on the active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode on the active layer, and forming a source interconnection on the source contact electrode. The step of forming the source interconnection includes the steps of forming a conductor film on the source contact electrode and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET further includes the step of performing annealing of heating the silicon carbide substrate to a temperature not lower than 50° C. after the step of processing the conductor film.

Abstract translation: 制造MOSFET的方法包括以下步骤：制备碳化硅衬底，在碳化硅衬底上形成有源层，在有源层上形成栅极氧化膜，在栅极氧化膜上形成栅电极，形成源极接触 电极，并且在源极接触电极上形成源极互连。 形成源极互连的步骤包括在源极接触电极上形成导体膜并通过用反应离子蚀刻蚀刻导体膜来处理导体膜的步骤。 然后，制造MOSFET的方法还包括在处理导体膜的步骤之后执行将碳化硅衬底加热到​​不低于50℃的温度的退火的步骤。

公开(公告)号：US20120292742A1

公开(公告)日：2012-11-22

申请号：US13469951

申请日：2012-05-11

Applicant: Satomi Itoh ,  Takeyoshi Masuda

Inventor： Satomi Itoh ,  Takeyoshi Masuda

IPC: H01L29/06

CPC classification number: H01L29/7802 ,  H01L21/8213 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

Abstract: A MOSFET includes a silicon carbide substrate, a buffer layer made of silicon carbide formed on the silicon carbide substrate, a drift layer made of silicon carbide of an n conductivity type formed on the buffer layer, a p type body region of a p conductivity type formed in the drift layer to include a main surface of the drift layer opposite to the buffer layer, a source contact electrode formed on the p type body region, and a drain electrode formed on a main surface of the silicon carbide substrate opposite to the buffer layer. A current path region having an impurity concentration higher than that of another region in the drift layer is formed in a region in the drift layer sandwiched between the buffer layer and the body region.

Abstract translation: MOSFET包括碳化硅衬底，由碳化硅衬底上形成的碳化硅制成的缓冲层，形成在缓冲层上的n导电型碳化硅的漂移层，形成为p型导电类型的ap型体区域 所述漂移层包括与所述缓冲层相对的所述漂移层的主表面，形成在所述p型体区上的源极接触电极，以及形成在所述碳化硅衬底的与所述缓冲层相反的主表面上的漏电极。 在夹在缓冲层和体区之间的漂移层中形成杂质浓度高于漂移层中的另一区域的电流路径区域。

公开(公告)号：US20120248461A1

公开(公告)日：2012-10-04

申请号：US13434233

申请日：2012-03-29

Applicant: Takeyoshi Masuda ,  Toru Hiyoshi ,  Keiji Wada

Inventor： Takeyoshi Masuda ,  Toru Hiyoshi ,  Keiji Wada

IPC: H01L29/24

CPC classification number: H01L21/28 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm−3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

Abstract translation: 在基板的主表面上外延形成碳化硅层。 碳化硅层设置有具有相对于主表面倾斜的侧壁的沟槽。 侧壁相对于{0001}面具有不小于50°且不超过65°的偏角。 栅极绝缘膜设置在碳化硅层的侧壁上。 碳化硅层包括：具有第一导电类型且面对栅电极的主体区域，栅极绝缘膜插入其间; 以及一对由身体区域彼此隔开并具有第二导电类型的区域。 体区的杂质密度为5×1016 cm -3以上。 这允许在抑制信道移动性的降低的同时增加设置阈值电压的自由度。