公开(公告)号：US20200066335A1

公开(公告)日：2020-02-27

申请号：US16544309

申请日：2019-08-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Chia-Fu Lee ,  Yi-Chun Shih ,  Hon-Jarn Lin ,  Ku-Feng Lin

IPC: G11C11/56 ,  G11C11/16

Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.

公开(公告)号：US10558525B2

公开(公告)日：2020-02-11

申请号：US15634876

申请日：2017-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Chia-Fu Lee ,  Chien-Yin Liu ,  Yi-Chun Shih ,  Kuan-Chun Chen ,  Hsueh-Chih Yang ,  Shih-Lien Linus Lu

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/15 ,  H03M13/19 ,  G11C29/42

Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.

公开(公告)号：US20190385656A1

公开(公告)日：2019-12-19

申请号：US16431158

申请日：2019-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.