公开(公告)号：US10679688B2

公开(公告)日：2020-06-09

申请号：US16142954

申请日：2018-09-26

Applicant: Samsung Electronics Co., LTD.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl

IPC: G11C11/22 ,  H01L27/11585 ,  H01L27/11502

Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

公开(公告)号：US20200158970A1

公开(公告)日：2020-05-21

申请号：US16749908

申请日：2020-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daniel N. Carothers ,  Titash Rakshit

IPC: G02B6/43 ,  G02B6/12 ,  G02B6/136 ,  G02B6/36 ,  H01S5/026

Abstract: A method for providing a vertical optical via for a semiconductor substrate is described. The semiconductor substrate has a front surface and a back side. A hard mask having an aperture therein is formed on the front surface. Part of the semiconductor substrate exposed by the aperture is removed to form a via hole. The via hole has a width not exceeding one hundred micrometers and a bottom. Cladding layer(s) and core layer(s) are provided in the via hole. The core layer(s) have at least a second index of refraction greater than that of the core layer(s). A portion of the semiconductor substrate including the back side is removed to expose a bottom portion of the core layer(s) and a bottom surface of the semiconductor substrate. The vertical optical via includes the cladding and core layers. The vertical optical via extends from the front surface to the bottom surface.

公开(公告)号：US20190392881A1

公开(公告)日：2019-12-26

申请号：US16290715

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan Hatcher ,  Jorge A. Kittl

IPC: G11C11/16 ,  G06N3/063 ,  G06F7/50 ,  H01L43/08 ,  H01L43/06 ,  H01L43/04 ,  H01L43/10

Abstract: A non-volatile data retention circuit includes a complementary latch configured to generate and store complementary non-volatile spin states corresponding to an input signal when in a write mode, and to concurrently generate a first charge current signal and a second charge current corresponding to the complementary non-volatile spin states when in read mode, and a differential amplifier coupled to the complementary latch and configured to generate an output signal based on the first and second charge current signals.

公开(公告)号：US20190318775A1

公开(公告)日：2019-10-17

申请号：US16142954

申请日：2018-09-26

Applicant: Samsung Electronics Co., LTD.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl

IPC: G11C11/22

Abstract: A memory cell and method for utilizing the memory cell are described. The memory cell includes at least one ferroelectric transistor (FE-transistor) and at least one selection transistor coupled with the FE-transistor. An FE-transistor includes a transistor and a ferroelectric capacitor for storing data. The ferroelectric capacitor includes ferroelectric material(s). In some aspects, the memory cell consists of a FE-transistor and a selection transistor. In some aspects, the transistor of the FE-transistor includes a source, a drain and a gate coupled with the ferroelectric capacitor. In this aspect, the selection transistor includes a selection transistor source, a selection transistor drain and a selection transistor gate. In this aspect, a write port of the memory cell is the selection transistor source or the selection transistor drain. The other of the selection transistor source and drain is coupled to the ferroelectric capacitor.

公开(公告)号：US20190280694A1

公开(公告)日：2019-09-12

申请号：US16137227

申请日：2018-09-20

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Titash Rakshit

IPC: H03K19/0944 ,  H01L29/51 ,  H01L27/118 ,  H03K19/20 ,  G06N3/063

Abstract: A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.

公开(公告)号：US20190154933A1

公开(公告)日：2019-05-23

申请号：US15965154

申请日：2018-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daniel N. Carothers ,  Titash Rakshit

IPC: G02B6/43 ,  G02B6/36

Abstract: A method for providing a vertical optical via for a semiconductor substrate is described. The semiconductor substrate has a front surface and a back side. A hard mask having an aperture therein is formed on the front surface. Part of the semiconductor substrate exposed by the aperture is removed to form a via hole. The via hole has a width not exceeding one hundred micrometers and a bottom. Cladding layer(s) and core layer(s) are provided in the via hole. The core layer(s) have at least a second index of refraction greater than that of the core layer(s). A portion of the semiconductor substrate including the back side is removed to expose a bottom portion of the core layer(s) and a bottom surface of the semiconductor substrate. The vertical optical via includes the cladding and core layers. The vertical optical via extends from the front surface to the bottom surface.

公开(公告)号：US20190080230A1

公开(公告)日：2019-03-14

申请号：US15849106

申请日：2017-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G06N3/063 ,  G06F7/544

Abstract: A hardware device and method for performing a multiply-accumulate operation are described. The device includes inputs lines, weight cells and output lines. The input lines receive input signals, each of which is has a magnitude and a phase and can represent a complex value. The weight cells couple the input lines with the output lines. Each of the weight cells has an electrical admittance corresponding to a weight. The electrical admittance is programmable and capable of being complex valued. The input lines, the weight cells and the output lines form a crossbar array. Each of the output lines provides an output signal. The output signal for an output line is a sum of an input signal for each of the input lines connected to the output line multiplied by the electrical admittance of each of the weight cells connecting the input lines to the output line.

公开(公告)号：US20190079701A1

公开(公告)日：2019-03-14

申请号：US15845985

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Vladimir Nikitin ,  Dmytro Apalkov

IPC: G06F3/06 ,  H01L21/3105 ,  H01L21/822 ,  H01L27/11578

Abstract: A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.

公开(公告)号：US20190026627A1

公开(公告)日：2019-01-24

申请号：US15891220

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G06N3/063 ,  G06N3/04

Abstract: A neuromorphic architecture for providing variable precision in a neural network, through programming. Logical pre-synaptic neurons are formed as configurable sets of physical pre-synaptic artificial neurons, logical post-synaptic neurons are formed as configurable sets of physical post-synaptic artificial neurons, and the logical pre-synaptic neurons are connected to the logical post-synaptic neurons by logical synapses each including a set of physical artificial synapses. The precision of the weights of the logical synapses may be varied by varying the number of physical pre-synaptic artificial neurons in each of the logical pre-synaptic neurons, and/or by varying the number of physical post-synaptic artificial neurons in each of the logical post-synaptic neurons.

公开(公告)号：US20190012593A1

公开(公告)日：2019-01-10

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/423

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.