Abstract:
A thin film transistor array panel, according to an embodiment of the present invention, includes a first data line, a second data line neighboring the first data line, a transistor disposed in a region between the first data line and the second data line, and a pixel electrode disposed close to the second data line among the first and second data lines. An extension of the pixel electrode may cross the second data line, thereby being connected to the transistor. Accordingly, it may not be necessary to use an additional connecting member between the pixel electrode and the data line such that the process may be shortened and the structure of the wiring may be simplified. Also, the spatial utility may be increased to improve the degree of integration.
Abstract:
A display device includes a pixel unit including a plurality of pixels coupled to a plurality of control lines and to a plurality of power lines to commonly receive same control signals and power source, a plurality of inlet pads positioned outside the pixel unit, the plurality of inlet pads being configured to apply the power source to the plurality of power lines, a pad bar electrically coupling the plurality of inlet pads, and a plurality of coupling patterns contacting end portions of the plurality of power lines and corresponding end portions of the pad bar, the plurality of coupling patterns electrically connecting the plurality of power lines and the pad bar, and one or more of the end portions of the pad bar and the ends portions of the plurality of power lines have different contact areas with the plurality of coupling patterns.
Abstract:
A scan driving device includes: a first node transmitted with a clock signal input to a first clock signal input terminal; a second node transmitted with an input signal according to a clock signal input to a second clock signal input terminal; a first transistor transmitting a power source voltage to an output terminal according to a voltage of the first node; a second transistor formed to transmit the clock signal input to the third clock signal input terminal to the output terminal according to the voltage of the second node; and a dummy transistor formed to transmit the clock signal input to the third clock signal input terminal to the output terminal according to the voltage of the second node. One of the second transistor and the dummy transistor is cut off.
Abstract:
In a color filter substrate and a liquid crystal display device including the same, the color filter substrate includes: a first black matrix not having an opening; a second black matrix having an opening; the first black matrix and the second black matrix being formed on a substrate; an auxiliary pattern disposed in the opening; a color filter covering the first and second black matrixes and formed in each of a plurality of pixels; an overcoat layer formed on the color filter; a first column spacer formed on the overcoat layer so as to correspond to the first black matrix; and a second column spacer formed above the auxiliary pattern so as to correspond to the second black matrix.
Abstract:
A liquid crystal display includes first and second insulating substrates facing each other, and a plurality of pixels comprising a plurality of rows and a plurality of columns and divided into a first pixel group comprising only the pixels on a first row and a second pixel group comprising each of the remaining pixels on second to last rows. The pixels of the first pixel group have a first opening ratio, and the pixels of the second pixel group have a second opening ratio different from the first opening ratio. The first opening ratio is smaller than the second opening ratio, and the first opening ratio is about 60% to about 80% of the second opening ratio; and the pixels of the first pixel group but not the pixels of the second pixel group have a light interception pattern in an opening portion.
Abstract:
A liquid crystal display includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the plurality of gate lines, a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines, and a plurality of pixel electrodes connected to the plurality of thin film transistors and arranged in a matrix, wherein each of the pixel electrodes includes a first side parallel to each gate line and a second side being shorter than the first side, the second side being formed next to the first side, wherein the plurality of pixel electrodes that are adjacent to each other in a column direction are connected to different data lines from each other.