公开(公告)号：US20200342928A1

公开(公告)日：2020-10-29

申请号：US16962309

申请日：2020-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE

IPC: G11C11/408 ,  H01L27/108

Abstract: A novel storage device and a novel semiconductor device are provided.In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.

公开(公告)号：US20250126843A1

公开(公告)日：2025-04-17

申请号：US18834020

申请日：2023-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10D30/67 ,  H01L23/528 ,  H10B12/00

Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. In each of the first to third transistors, the side surfaces of a metal oxide are covered with a source electrode and a drain electrode. The second and third transistors share the metal oxide. The capacitor is provided above the first to third transistors. A conductor including a region functioning as a write bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the first transistor. A conductor including a region functioning as a read bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the third transistor. The other of the source electrode and the drain electrode of the first transistor and a gate of the second transistor are electrically connected to one electrode of the capacitor.

公开(公告)号：US20250126795A1

公开(公告)日：2025-04-17

申请号：US19001855

申请日：2024-12-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Hitoshi KUNITAKE

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device with high storage capacity is provided. The semiconductor device includes first to sixth insulators, first to third conductors, and first to third material layers. The first conductor overlaps with a first insulator and a first material layer. A first region of the first material layer overlaps with a second material layer, a second conductor, a second insulator, and a third insulator. The third material layer is positioned in a region including a second region of the first material layer and top surfaces of the second material layer, the second conductor, the second insulator, and the third insulator; a fourth insulator is positioned over the third material layer; the sixth insulator is positioned over the fourth insulator; and a fifth insulator is positioned over the sixth insulator. The third conductor is positioned over the fifth insulator overlapping with the second region of the first material layer. The first to third material layers include oxide containing indium, an element M (M is aluminum, gallium, tin, or titanium), and zinc.

公开(公告)号：US20250126777A1

公开(公告)日：2025-04-17

申请号：US18730461

申请日：2023-01-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10B12/00

Abstract: An electronic device including a first conductor, a second conductor, a first insulator, a second insulator, and a connection electrode is provided. The first insulator is provided over the first conductor and has a first opening overlapping with the first conductor. The second conductor is provided over the first insulator and has a second opening overlapping with the first conductor. The second insulator is provided over the second conductor and has a third opening overlapping with the first conductor. The second opening has a portion having a width smaller than a width of the third opening. The connection electrode is positioned inside the first opening, the second opening, and the third opening and is in contact with the top surface of the first conductor. The connection electrode includes a region in contact with part of the top surface and part of the side surface of the second conductor.

公开(公告)号：US20250120182A1

公开(公告)日：2025-04-10

申请号：US18834279

申请日：2023-02-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10D88/00 ,  H10D62/80

Abstract: A semiconductor device that can be scaled down or highly integrated is to be provided. The semiconductor device includes a first conductor, a second conductor, a first insulator, a first transistor over the first insulator, and a second insulator over the first transistor. The first transistor includes a first metal oxide, a third conductor and a fourth conductor electrically connected to the first metal oxide, a third insulator over the first metal oxide, and a fifth conductor over the third insulator. The top surface of the fifth conductor includes a region in contact with the second insulator. The first conductor includes a portion positioned on an inner side of an opening of the first insulator, a region in contact with the side surface of the third conductor, and a portion positioned on an inner side of an opening of the second insulator. The second conductor includes a region in contact with the top surface of the fourth conductor, and a portion positioned on an inner side of an opening of the second insulator. The top surface of the first conductor is level or substantially level with the top surface of the second conductor.

公开(公告)号：US20250113545A1

公开(公告)日：2025-04-03

申请号：US18833507

申请日：2023-01-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10D30/67 ,  H10B12/00 ,  H10D86/40

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor and a second transistor over an insulating surface; the first transistor and the second transistor share a metal oxide and a first conductor over the metal oxide; the first transistor includes a second conductor and a first insulator over the metal oxide and a third conductor over the first insulator; the second transistor includes a fourth conductor and a second insulator over the metal oxide and a fifth conductor over the second insulator; the first insulator is positioned in a region between the first conductor and the second conductor; the metal oxide and the third conductor overlap with each other with the first insulator therebetween; the second insulator is positioned in a region between the first conductor and the fourth conductor; and the metal oxide and the fifth conductor overlap with each other with the second insulator therebetween.

公开(公告)号：US20250015193A1

公开(公告)日：2025-01-09

申请号：US18748238

申请日：2024-06-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Fumito ISAKA ,  Yuichi SATO ,  Toshikazu OHNO ,  Hitoshi KUNITAKE ,  Tsutomu MURAKAWA

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H10B12/00 ,  H10K59/121

Abstract: Provided are a transistor with favorable electrical characteristics, a transistor with a high on-state current, a transistor with low parasitic capacitance, or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. An oxide semiconductor layer included in the transistor, the semiconductor device, or the memory device includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron 10 microscope, bright spots arranged in a layered manner in a direction parallel to the surface are observed in each of the first region, the second region, and the third region.

公开(公告)号：US20250015089A1

公开(公告)日：2025-01-09

申请号：US18712398

申请日：2022-11-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hitoshi KUNITAKE ,  Ryota HODO ,  Tsutomu MURAKAWA

IPC: H01L27/12

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a first metal oxide, a first conductor, a second conductor, and a third conductor. The first metal oxide includes a first depressed portion, a second depressed portion, and a third depressed portion positioned between the first depressed portion and the second depressed portion. The first conductor is provided to fill the first depressed portion, and the second conductor is provided to fill the second depressed portion. A top surface of the first conductor and a top surface of the second conductor are level with or substantially level with a top surface of the first metal oxide. The first insulator is provided inside the third depressed portion. The third conductor is provided over the first insulator and includes a region overlapping with the first metal oxide with the first insulator therebetween.

公开(公告)号：US20240147708A1

公开(公告)日：2024-05-02

申请号：US18288413

申请日：2022-04-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE

IPC: H10B12/00 ,  H01L25/065 ,  H10B10/00 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B12/50 ,  H01L25/0657 ,  H10B10/125 ,  H10B10/18 ,  H10B12/33 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first substrate provided with a first peripheral circuit having a function of driving a first memory cell and a first memory cell layer including a second substrate and a first element layer including the first memory cell. The first memory cell includes a first transistor and a first capacitor. The first transistor includes a semiconductor layer including a metal oxide in its channel formation region. The first memory cell layer is provided to be stacked over the first substrate in a direction perpendicular or substantially perpendicular to a surface of the first substrate. The second substrate includes a circuit for performing writing of data to or reading of data from the first memory cell. The first peripheral circuit and the first memory cell are electrically connected to each other through a first through electrode provided in the second substrate and the first element layer.

公开(公告)号：US20230329002A1

公开(公告)日：2023-10-12

申请号：US18023618

申请日：2021-08-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yasuhiro JINBO ,  Hitoshi KUNITAKE ,  Haruyuki BABA ,  Yuki ITO ,  Fumito ISAKA ,  Kazuki TANEMURA ,  Yasumasa YAMANE ,  Tatsuya ONUKI

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. A first conductor is formed over a substrate, a ferroelectric layer is formed over the first conductor, a second conductor is formed over the ferroelectric layer while substrate heating is performed, the ferroelectric layer includes hafnium oxide and zirconium oxide, and heat treatment at 500° C. or higher is not performed after the formation of the second conductor.