公开(公告)号：US20130235639A1

公开(公告)日：2013-09-12

申请号：US13869086

申请日：2013-04-24

Applicant: QUALCOMM INCORPORATED

Inventor： Kangho Lee ,  Taehyun Kim ,  Xia Li ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C5/02 ,  G11C5/08

CPC classification number: G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

Abstract: A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Abstract translation: 大型存储器阵列包括a。 均匀大小的虚拟位单元和有源位单元的统一模式。 大规模存储器阵列中的子阵列由虚拟位单元分隔开。 信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。 类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。