公开(公告)号：US5289431A

公开(公告)日：1994-02-22

申请号：US952929

申请日：1992-09-29

Applicant: Yasuhiro Konishi

Inventor： Yasuhiro Konishi

IPC: G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  H01L27/10 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C11/409 ,  G11C11/4094

Abstract: In a DRAM of separated I/O type, column selecting lines for reading data and column selecting lines for writing data are provided independently from each other. An addition circuit is provided corresponding to each memory cell array block for precharging, when that memory cell array is not selected, a read line pair corresponding that memory cell array block to the same potential Vb1 as that of the bit lines equalized by an equalizer circuit. Both in data reading and writing operations, current does not flow between any equalizer circuit and the write data line pair provided corresponding to each unselected memory cell array block in spite of the fact that a transistor for write selection is not provided in each bit line pair.

Abstract translation: 在分离的I / O型的DRAM中，独立地提供用于读取数据的列选择线和用于写入数据的列选择线。 对应于每个用于预充电的存储单元阵列块提供加法电路，当没有选择该存储单元阵列时，将与该存储单元阵列块相对应的读线对与由均衡电路均衡的位线相同的电位Vb1 。 在数据读取和写入操作中，尽管在每个位线对中没有提供用于写入选择的晶体管的事实，但是在任何均衡器电路和与每个未选择的存储单元阵列块相对应的写入数据线对之间，电流不会流动 。

公开(公告)号：US4984210A

公开(公告)日：1991-01-08

申请号：US565400

申请日：1990-08-10

Applicant: Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Youichi Tobita

Inventor： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Youichi Tobita

IPC: G11C11/407 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/406 ,  G11C11/4076

Abstract: In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.

公开(公告)号：US4954992A

公开(公告)日：1990-09-04

申请号：US269757

申请日：1988-11-08

Applicant: Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

Inventor： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/1057 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/062 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

Abstract: A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.

Abstract translation: 一种动态随机存取存储器件包括一对写入数据传送总线，用于传送要被写入的数据，一对读出数据传输总线，用于传送要被读取的数据，附加地和独立于写入数据传输总线 对和由CMOS晶体管形成的多个电流镜型读出放大器，并且每个放大器设置在位线对和读出数据传输总线对之间，并且具有连接到相应位线对和读出数据的输入节点 传输总线对形成其输出节点。 响应于比传统的触发器型读出放大器被激活的时间早的列解码器的输出，CMOS晶体管的电流镜式读出放大器被激活。

公开(公告)号：US4943960A

公开(公告)日：1990-07-24

申请号：US337976

申请日：1989-04-14

Applicant: Takahiro Komatsu ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi

Inventor： Takahiro Komatsu ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094

CPC classification number: G11C11/4094 ,  G11C11/406 ,  G11C11/4074

Abstract: There is disclosed a dynamic random access memory device of the type capable of periodic self-refresh cycles of operation. The DRAM includes the detector circuit for detecting the designation of the self-refresh mode and a voltage generator circuit for generating a voltage to precharge the bit line pair. During the self-controlled refresh cycle, the bit line pair is equalized and precharged to a voltage lower than Vcc/2. When it is attempted to set the time interval between the self-refresh cycles in order to reduce current consumption, the level of voltage stored in the memory cell capacitor tends to decrease due to charge leakage. However, it is implemented to provide and keep a potential difference between the precharge voltage on the bit line pair and the voltage stored in the capacitor thereby to secure the desired sensing margin for the sense amplifier.

Abstract translation: 公开了一种能够进行周期性自刷新操作周期的动态随机存取存储器件。 DRAM包括用于检测自刷新模式的指定的检测器电路和用于产生用于对位线对预充电的电压的电压发生器电路。 在自控刷新周期期间，位线对被均衡并预充电到低于Vcc / 2的电压。 当为了减少电流消耗而尝试设置自刷新周期之间的时间间隔时，由于电荷泄漏，存储在存储单元电容器中的电压电平趋于降低。 然而，实现了提供并保持位线对上的预充电电压和存储在电容器中的电压之间的电位差，从而确保感测放大器所需的感测余量。

公开(公告)号：US4837747A

公开(公告)日：1989-06-06

申请号：US126349

申请日：1987-11-30

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Yuto Ikeda ,  Kazuhiro Tsukamoto ,  Masaki Shimoda

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Yuto Ikeda ,  Kazuhiro Tsukamoto ,  Masaki Shimoda

IPC: G11C8/12 ,  G11C29/00

CPC classification number: G11C29/806 ,  G11C8/12

Abstract: A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals "0". The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals "1". A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.

Abstract translation: 存储单元阵列被分成四个块＃1到＃4。 当行地址信号RA8等于“0”时，块＃1和＃3被操作。 当行地址信号RA8等于“1”时，块＃2和＃4被操作。 在每个块中提供备用行子解码器。 块＃1和＃2中的备用行子解码器通过单个备用解码器选择线连接到备用主主解码器。 块＃2和＃4中的备用行子解码器通过另一个备用解码器选择线连接到另一备用行主解码器。 备用主解码器响应于行地址信号RA8和行地址信号RA2，RA2。 。 。 ，RA7，RA7，用于在处于操作状态的块中操作备用行子解码器。

公开(公告)号：US4809230A

公开(公告)日：1989-02-28

申请号：US938065

申请日：1986-12-04

Applicant: Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

Inventor： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

IPC: G11C11/407 ,  G11C11/34 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/00 ,  G11C7/00 ,  G11C11/40

CPC classification number: G11C11/4076 ,  G11C11/4094

Abstract: A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

Abstract translation: MOS动态型RAM包括存储单元（10），虚设单元（11），位线对（BL，＆amp; B和B），字线（WL），虚拟字线（DWL）和读出放大器（12）。 在非有效周期中，每对位线（BL，＆amp; B和B）的电位在电源电位VCC的1/2处被预充电。 每个读出放大器（12）在非活动周期之后的有效周期中工作，而每个有源上拉电路（13）将该对位线中较高一级的电位上拉至VCC。 该活动周期由内部RAS内部信号定义，该内部RAS内部信号由NAND电路（27）响应于通过延迟电路（20）延迟外部＆upbar＆R信号而获得的外部＆upbar＆R信号和＆upbar＆R信号产生的内部RAS内部信号， 并且具有通过将外部＆upbar＆R信号的后沿延迟预定周期而获得的后沿。

公开(公告)号：US20130173106A1

公开(公告)日：2013-07-04

申请号：US13811976

申请日：2011-07-25

Applicant: Yasuhiro Konishi

Inventor： Yasuhiro Konishi

IPC: B60W20/00 ,  B60W10/08 ,  B60W10/06

CPC classification number: B60W20/11 ,  B60K6/46 ,  B60L3/12 ,  B60L11/005 ,  B60L11/123 ,  B60L11/1816 ,  B60L2210/30 ,  B60L2210/40 ,  B60L2250/10 ,  B60L2250/16 ,  B60W10/06 ,  B60W10/08 ,  B60W20/00 ,  B60W20/18 ,  B60W50/0097 ,  B60W50/14 ,  B60W2050/146 ,  B60W2510/0623 ,  B60W2550/402 ,  B60W2560/02 ,  B60W2560/04 ,  F02D29/02 ,  F02M37/0076 ,  Y02T10/6217 ,  Y02T10/6269 ,  Y02T10/7005 ,  Y02T10/7022 ,  Y02T10/7072 ,  Y02T10/7077 ,  Y02T10/7241 ,  Y02T90/127 ,  Y02T90/14 ,  Y10S903/93

Abstract: The present invention concerns a vehicle including a fuel tank, an engine to which fuel is supplied from the fuel tank, and a control device. The control device is characterized by notifying a refueling instruction corresponding to a use history of the vehicle. According to the present invention, the supply of extra fuel that can be degraded in the fuel tank can be prevented since a necessary refueling instruction is notified in accordance with the use history of the vehicle.

Abstract translation: 本发明涉及一种包括燃料箱，从燃料箱供给燃料的发动机和控制装置的车辆。 控制装置的特征在于通知与车辆的使用历史对应的加油指令。 根据本发明，由于根据车辆的使用历史来通知必要的加油指示，因此能够防止在燃料箱中劣化的额外燃料的供给。

公开(公告)号：US08319617B2

公开(公告)日：2012-11-27

申请号：US12584869

申请日：2009-09-14

Applicant: Kenichi Ohshima ,  Shigenobu Saigusa ,  Yasuhiro Konishi

Inventor： Kenichi Ohshima ,  Shigenobu Saigusa ,  Yasuhiro Konishi

IPC: B60Q1/00

CPC classification number: B60R1/12 ,  B60R1/00 ,  B60R2001/1253 ,  B60R2300/102 ,  B60R2300/105

Abstract: A vehicle surroundings monitoring apparatus includes: a plurality of imaging units which capture an external region of a present-vehicle and output images; a display unit which is installed in an interior of the present-vehicle; a selector which selects an image to be displayed on the display unit from the images output from the imaging units; and a display control unit which displays the images output from the imaging units on the display unit so as to be switched in accordance with a selection by the selector and displays an image indicator display indicating a display region in the external region of the present-vehicle corresponding to the images so as to be switched by the selector on the display unit.

Abstract translation: 车辆周边监视装置包括：多个成像单元，其捕获本车辆的外部区域并输出图像; 安装在本车内部的显示单元; 选择器，其从从所述成像单元输出的图像中选择要在所述显示单元上显示的图像; 以及显示控制单元，其将根据所述选择器的选择切换的所述成像单元输出的图像显示在所述显示单元上，并且在所述当前车辆的外部区域中显示指示显示区域的图像指示符显示器 对应于图像，以便由显示单元上的选择器切换。

公开(公告)号：US07787475B2

公开(公告)日：2010-08-31

申请号：US11885942

申请日：2006-03-20

Applicant: Shu Hagiwara ,  Suguru Nishio ,  Shingo Tsunoda ,  Yasuhiro Konishi ,  Masateru Gohno

Inventor： Shu Hagiwara ,  Suguru Nishio ,  Shingo Tsunoda ,  Yasuhiro Konishi ,  Masateru Gohno

IPC: H04L12/56

CPC classification number: H04W16/14 ,  H04L45/24 ,  H04W28/06 ,  H04W28/14 ,  H04W74/08 ,  H04W88/04

Abstract: A communication apparatus having a temporary managing portion for controlling a temporary memory, a main managing portion for controlling a main memory and an operation control portion. The operation control portion causes the temporary managing portion and the main managing portion to utilize the state information or the history and state information for obtaining probability of deletion or transmission and probability of delay with regard to each data frame of framed data for discharge and to control, on the basis of the obtained probability of deletion or transmission and the obtained probability of delay, deletion or transmission of the data frame of the framed data for discharge and delay for transmission of the data frame of the framed data for discharge on the occasion of the transmission thereof.

Abstract translation: 具有用于控制临时存储器的临时管理部分，用于控制主存储器的主管理部分和操作控制部分的通信装置。 操作控制部分使得临时管理部分和主管理部分利用状态信息或历史和状态信息来获取关于用于放电的成帧数据的每个数据帧的删除或传输的概率和延迟的概率，并且控制 基于所获得的删除或传输的概率以及获得的用于放电的成帧数据的数据帧的延迟，删除或传输的概率，以及用于发送用于放电的成帧数据的数据帧的延迟， 其传输。

公开(公告)号：US20100070139A1

公开(公告)日：2010-03-18

申请号：US12584734

申请日：2009-09-11

Applicant: Kenichi Ohshima ,  Yukihiro Fujiwara ,  Yoshitaka Katashima ,  Hiroyuki Kawagoe ,  Shigenobu Saigusa ,  Yasushi Shoda ,  Manabu Shimizu ,  Yasuhiro Konishi

Inventor： Kenichi Ohshima ,  Yukihiro Fujiwara ,  Yoshitaka Katashima ,  Hiroyuki Kawagoe ,  Shigenobu Saigusa ,  Yasushi Shoda ,  Manabu Shimizu ,  Yasuhiro Konishi

IPC: G06F7/00

CPC classification number: B62D15/0275 ,  B60R1/00 ,  B60R2300/105 ,  B60R2300/303 ,  B60R2300/305 ,  B60R2300/607 ,  B60R2300/806 ,  B62D15/028

Abstract: The vehicle maneuver assistance device includes: a plurality of external environment imaging units; a converter that performs a view point conversion; a display unit provided in an interior of the present-vehicle; a steering angle status value detector which detects status values of the steering angle representing an actual steering angle of the present-vehicle, and outputs a steering angle status value; a display controller that causes the display unit to display the converted image, and, overlaid thereon, a guidance display which assists a parking maneuver of the present-vehicle, wherein the display controller controls the guidance display according to the steering angle status value, so that the guidance display includes: an initial positioning guide line representing an initial location of the present-vehicle at the beginning of the parking maneuver; and a steering-switching start positioning guide line representing a starting location of a quick steering direction switching.

Abstract translation: 车辆操纵辅助装置包括：多个外部环境成像单元; 执行视点转换的转换器; 设置在本车内部的显示单元; 转向角状态值检测器，其检测表示本车辆的实际转向角的转向角的状态值，并输出转向角状态值; 显示控制器，其使显示单元显示转换的图像，并且覆盖有辅助本车的停车操作的引导显示，其中显示控制器根据转向角状态值来控制引导显示，因此， 引导显示包括：在停车操作开始时代表当前车辆的初始位置的初始定位引导线; 以及表示快速转向方向切换的起始位置的转向切换开始定位引导线。