知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

89 records (took 0.022 seconds)

    SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES
    73.
    发明申请
    SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES 有权
    具有不同栅极氧化物厚度的半导体器件

    公开(公告)号：US20150069525A1

    公开(公告)日：2015-03-12

    申请号：US14541182

    申请日：2014-11-14

    Applicant: International Business Machines Corporation

    Inventor： Charlotte D. Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

    IPC: H01L27/088 ,  H01L29/423

    CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

    Abstract translation: 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

    FIN Field Effect Transistors Having Multiple Threshold Voltages
    74.
    发明申请
    FIN Field Effect Transistors Having Multiple Threshold Voltages 审中-公开
    具有多个阈值电压的FIN场效应晶体管

    公开(公告)号：US20150021699A1

    公开(公告)日：2015-01-22

    申请号：US13945095

    申请日：2013-07-18

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  Michael P. Chudzik ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

    IPC: H01L27/088 ,  H01L21/28

    CPC classification number: H01L27/0886 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4908

    Abstract: A high dielectric constant (high-k) gate dielectric layer is formed on semiconductor fins including one or more semiconductor materials. A patterned diffusion barrier metallic nitride layer is formed to overlie at least one channel, while not overlying at least another channel. A threshold voltage adjustment oxide layer is formed on the physically exposed portions of the high-k gate dielectric layer and the diffusion barrier metallic nitride layer. An anneal is performed to drive in the material of the threshold voltage adjustment oxide layer to the interface between the intrinsic channel(s) and the high-k gate dielectric layer, resulting in formation of threshold voltage adjustment oxide portions. At least one workfunction material layer is formed, and is patterned with the high-k gate dielectric layer and the threshold voltage adjustment oxide portions to form multiple types of gate stacks straddling the semiconductor fins.

    Abstract translation: 在包括一种或多种半导体材料的半导体鳍片上形成高介电常数（高k）栅极电介质层。 形成图案化扩散阻挡金属氮化物层以覆盖至少一个通道，而不覆盖至少另一个通道。 在高k栅极电介质层和扩散阻挡金属氮化物层的物理暴露部分上形成阈值电压调整氧化物层。 执行退火以将阈值电压调节氧化物层的材料驱动到本征通道和高k栅极电介质层之间的界面，从而形成阈值电压调节氧化物部分。 形成至少一个功函数材料层，并用高k栅极介电层和阈值电压调整氧化物部分进行图案化以形成跨越半导体鳍片的多种类型的栅叠层。

    SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT
    75.
    发明申请
    SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT 有权
    金属门与铝包含金属层用于阈值电压转换

    公开(公告)号：US20130175642A1

    公开(公告)日：2013-07-11

    申请号：US13775430

    申请日：2013-02-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

    IPC: H01L29/51 ,  H01L29/40

    CPC classification number: H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

    Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

    Abstract translation: 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

    Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages
    76.
    发明授权
    Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages 有权

    公开(公告)号：US10985075B2

    公开(公告)日：2021-04-20

    申请号：US16157325

    申请日：2018-10-11

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Unoh Kwon ,  Vijay Narayanan

    IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28

    Abstract: Embodiments of the invention are directed to a method that includes forming a first channel fin in an n-type region of a substrate, forming a second channel fin in a p-type region of the substrate, and depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric, the first fin in the n-type region, and the second fin in the p-type region. The work function metal stack over the gate dielectric and the first fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes at least one shared layer of work function metal that is shared with the second work function metal stack.

    STRUCTURE AND METHOD TO SUPPRESS WORK FUNCTION EFFECT BY PATTERNING BOUNDARY PROXIMITY IN REPLACEMENT METAL GATE
    77.
    发明申请
    STRUCTURE AND METHOD TO SUPPRESS WORK FUNCTION EFFECT BY PATTERNING BOUNDARY PROXIMITY IN REPLACEMENT METAL GATE 审中-公开

    公开(公告)号：US20190259754A1

    公开(公告)日：2019-08-22

    申请号：US16401141

    申请日：2019-05-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ruqiang Bao ,  Unoh Kwon ,  Kai Zhao

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49

    Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

Patent Agency Ranking