公开(公告)号：US20070235738A1

公开(公告)日：2007-10-11

申请号：US11224286

申请日：2005-09-13

Applicant: Young-gu Jin ,  Hyo-sug Lee ,  Sung-hoon Lee

Inventor： Young-gu Jin ,  Hyo-sug Lee ,  Sung-hoon Lee

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L33/18 ,  H01L33/08 ,  H01L33/20

Abstract: A nanowire light emitting device and method of fabricating the same. The nanowire light emitting device includes: a substrate; a first electrode layer formed on the substrate; a plurality of nanowires vertically formed on the first electrode layer, the nanowire having a p-type doped portion and an n-type doped portion formed separately from each other on both sides thereof; a light emitting layer formed between the p-type doped portion and the n-type doped portion; and a second electrode layer formed on the nanowires, wherein the p-type doped portion is formed by chemically binding a radical having an only half-occupied outermost orbital shell to a corresponding surface of the respective nanowires so as to donate an electron to the radical.

Abstract translation: 纳米线发光器件及其制造方法。 纳米线发光器件包括：衬底; 形成在所述基板上的第一电极层; 在所述第一电极层上垂直形成的多个纳米线，所述纳米线的两侧分别形成有p型掺杂部和n型掺杂部， 在p型掺杂部分和n型掺杂部分之间形成的发光层; 以及形成在所述纳米线上的第二电极层，其中所述p型掺杂部分通过将仅具有半占据的最外轨道壳的基团化学结合到相应纳米线的相应表面而形成，以便向所述基团 。

公开(公告)号：US07125770B2

公开(公告)日：2006-10-24

申请号：US11373152

申请日：2006-03-13

Applicant: Sung Hoon Lee

Inventor： Sung Hoon Lee

IPC: H01L21/8247

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

Abstract: The present invention relates to a gate structure of a flash memory cell and method of forming the same, and method of forming a dielectric film. The method of forming the dielectric film in the flash memory cell comprises the steps of preparing a wafer including a tunnel oxide film formed in a given region of a semiconductor substrate, a polysilicon film formed on the tunnel oxide film, and an oxide film and a silicon nitride film formed on the polysilicon film; preparing a work cell in which a voltage is applied to the rear side of the semiconductor substrate used as a work electrode in which the silicon nitride film is formed, a relative electrode and a reference electrode are kept by a given distance so that they can be immersed in electrolyte, and in which an ultraviolet rays source is formed on an upper side to illuminate an ultraviolet rays to a work electrode; and performing electro-chemical etch using silicon dissociation reaction for the wafer mounted on the work cell to form porosities in the silicon nitride film.

Abstract translation: 本发明涉及闪存单元的栅极结构及其形成方法，以及形成电介质膜的方法。 在闪速存储单元中形成电介质膜的方法包括以下步骤：制备包括在半导体衬底的给定区域中形成的隧道氧化物膜的晶片，形成在隧道氧化物膜上的多晶硅膜，以及氧化物膜和 形成在多晶硅膜上的氮化硅膜; 准备在用作形成氮化硅膜的工作电极的半导体衬底的后侧施加电压的工作单元，相对电极和参考电极保持给定距离，使得它们可以是 浸入电解质中，并且在上侧形成紫外线源以向工作电极照射紫外线; 以及使用硅解离反应对安装在工作单元上的晶片进行电化学蚀刻，以在氮化硅膜中形成孔隙率。

公开(公告)号：US07012655B2

公开(公告)日：2006-03-14

申请号：US10742917

申请日：2003-12-23

Applicant: Dong Jae You ,  Nam Do Son ,  Sung Hoon Lee

Inventor： Dong Jae You ,  Nam Do Son ,  Sung Hoon Lee

IPC: G02F1/1335

CPC classification number: G02F1/13338 ,  G02F1/133553 ,  G02F1/133615

Abstract: An LCD device with a digitizer and a method for manufacturing the same is disclosed, which has a stable insertion structure of a digitizer to an LCM, thereby obtaining thin profile and lightness of the LCD device, and improving yield. Also, in the LCD device with the digitizer according to the present invention, a reflecting means is formed for being integrated with the digitizer.

Abstract translation: 公开了一种具有数字化仪的LCD装置及其制造方法，其具有数字化仪对LCM的稳定的插入结构，从而获得LCD装置的薄型和亮度，并提高成品率。 此外，在根据本发明的具有数字化仪的LCD装置中，形成用于与数字化仪一体化的反射装置。

公开(公告)号：US20150069480A1

公开(公告)日：2015-03-12

申请号：US14203400

申请日：2014-03-10

Applicant: Hiroyuki KANAYA ,  Dong Jun KIM ,  Sung Hoon LEE

Inventor： Hiroyuki KANAYA ,  Dong Jun KIM ,  Sung Hoon LEE

IPC: H01L27/22 ,  H01L43/12

CPC classification number: H01L27/228 ,  G11C7/18 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory includes a cell transistor including a first source/drain diffusion layer and a second source/drain diffusion layer, a first contact on the first source/drain diffusion layer, a memory element on the first contact, and a second contact on the second source/drain diffusion layer, the second contact including a first plug on the second source/drain diffusion layer, and a second plug on the first plug.

Abstract translation: 根据一个实施例，磁存储器包括单元晶体管，其包括第一源极/漏极扩散层和第二源极/漏极扩散层，第一源极/漏极扩散层上的第一触点，第一触点上的存储元件，以及 在第二源/漏扩散层上的第二触点，第二触点包括在第二源极/漏极扩散层上的第一插头和第一插头上的第二插头。

公开(公告)号：US20140252679A1

公开(公告)日：2014-09-11

申请号：US14197498

申请日：2014-03-05

Applicant: Eun Soo HWANG ,  Eui Sun CHOI ,  Sung Hoon LEE

Inventor： Eun Soo HWANG ,  Eui Sun CHOI ,  Sung Hoon LEE

IPC: B29C59/04

CPC classification number: B29C59/046 ,  B29C59/026 ,  B29C2035/0827 ,  G03F7/0002

Abstract: A large-scale imprint apparatus includes a roll-to-roll unit configured to wind or rewind a flexible substrate, a stage arranged adjacent to a winding path of the flexible substrate, the stage being configured to support a stamp master with a master pattern or to support a substrate, and a stamping pressing unit arranged adjacent to the stage, the stamping pressing unit being configured to press the flexible substrate against the stamp master or against the substrate.

Abstract translation: 大型压印装置包括卷绕单元，其构造成卷绕或倒回柔性基板，邻近柔性基板的卷绕路径布置的台，该台被配置为支撑具有主图案的印模主体， 支撑基板和邻近台架设置的冲压单元，所述冲压单元构造成将柔性基板压靠在压模母板上或抵靠基板上。

公开(公告)号：US08785912B2

公开(公告)日：2014-07-22

申请号：US13225988

申请日：2011-09-06

Applicant: Hyun-jong Chung ,  Jae-hong Lee ,  Jae-ho Lee ,  Hyung-cheol Shin ,  Sun-ae Seo ,  Sung-hoon Lee ,  Jin-seong Heo ,  Hee-jun Yang

Inventor： Hyun-jong Chung ,  Jae-hong Lee ,  Jae-ho Lee ,  Hyung-cheol Shin ,  Sun-ae Seo ,  Sung-hoon Lee ,  Jin-seong Heo ,  Hee-jun Yang

IPC: H01L29/775 ,  B82Y99/00

CPC classification number: H01L29/1606 ,  H01L29/41733 ,  H01L29/66045 ,  H01L29/778 ,  H01L29/78684 ,  H01L29/78696

Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.

Abstract translation: 石墨烯电子器件可以包括衬底上的栅极电极，覆盖栅电极的第一栅极绝缘膜，衬底上的多个石墨烯沟道层，多个石墨烯沟道层之间的第二栅极绝缘膜，以及源电极和 连接到所述多个石墨烯通道层中的每一个的两个边缘的漏电极。

公开(公告)号：US08728880B2

公开(公告)日：2014-05-20

申请号：US13329842

申请日：2011-12-19

Applicant: Hyun-jong Chung ,  Jin-seong Heo ,  Hee-jun Yang ,  Sun-ae Seo ,  Sung-hoon Lee

Inventor： Hyun-jong Chung ,  Jin-seong Heo ,  Hee-jun Yang ,  Sun-ae Seo ,  Sung-hoon Lee

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/66477 ,  H01L29/42384 ,  H01L29/775 ,  H01L29/78684

Abstract: A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.

Abstract translation: 石墨烯电子器件包括在衬底上的石墨烯通道层，石墨烯通道层的端部上的源电极和在石墨烯通道层的另一端部上的漏电极，石墨烯通道层上的栅极氧化物 源电极和漏电极，栅极氧化物上的栅电极。 栅极氧化物具有与源电极和漏电极之间的石墨烯沟道层基本相同的形状。

公开(公告)号：US08692223B2

公开(公告)日：2014-04-08

申请号：US13596807

申请日：2012-08-28

Applicant: Ji-Won Moon ,  Moon-Sig Joo ,  Sung-Hoon Lee ,  Jung-Nam Kim

Inventor： Ji-Won Moon ,  Moon-Sig Joo ,  Sung-Hoon Lee ,  Jung-Nam Kim

IPC: H01L47/00

CPC classification number: H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1641

Abstract: A resistance variable memory device includes: a first electrode; a second electrode; a resistance variable layer interposed between the first electrode and the second electrode; and nano particles that are disposed in the resistance variable layer and have a lower dielectric constant than the resistance variable layer.

Abstract translation: 电阻可变存储器件包括：第一电极; 第二电极; 介于所述第一电极和所述第二电极之间的电阻变化层; 和纳米颗粒，其设置在电阻变化层中并具有比电阻变化层低的介电常数。

公开(公告)号：US08539143B2

公开(公告)日：2013-09-17

申请号：US13421964

申请日：2012-03-16

Applicant: Jin-Hyeok Choi ,  Sung-Hoon Lee ,  Si-Hoon Hong ,  Tae-Keun Jeon

Inventor： Jin-Hyeok Choi ,  Sung-Hoon Lee ,  Si-Hoon Hong ,  Tae-Keun Jeon

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0646

Abstract: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

Abstract translation: 提供了一种存储器系统，包括主处理器和连接到主处理器的多个级联连接的存储卡。 每个存储卡在存储器系统的初始化之前存储相同的默认相对卡地址（RCA）。 主处理器配置为使用默认RCA顺序访问每个存储卡，并且在每次顺序访问时将默认RCA更改为唯一的RCA。

公开(公告)号：US08420532B2

公开(公告)日：2013-04-16

申请号：US11962442

申请日：2007-12-21

Applicant: Sung Hoon Lee

Inventor： Sung Hoon Lee

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/311

CPC classification number: H01L21/76808 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11517

Abstract: The present invention relates to a method of fabricating a semiconductor device. According to the method, a first insulating layer having a contact hole formed therein is formed over a semiconductor substrate. A second insulating layer is gap filled within the contact hole. A third insulating layer having a trench formed therein is formed over the semiconductor substrate including the contact hole. The second insulating layer gap filled within the contact hole is removed. A contact plug and a bit line are formed within the contact hole and the trench.

Abstract translation: 本发明涉及半导体器件的制造方法。 根据该方法，在半导体衬底上形成有形成有接触孔的第一绝缘层。 第二绝缘层在接触孔内填充间隙。 形成有沟槽的第三绝缘层形成在包括接触孔的半导体衬底的上方。 去除填充在接触孔内的第二绝缘层间隙。 接触插塞和位线形成在接触孔和沟槽内。