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公开(公告)号：US11574176B2
公开(公告)日：2023-02-07
申请号：US16788737
申请日：2020-02-12
发明人： John Paul Lesso
摘要： The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.
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72.发明授权公开(公告)号：US11552649B1
公开(公告)日：2023-01-10
申请号：US17541596
申请日：2021-12-03
发明人： Ramin Zanbaghi
摘要： A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.
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公开(公告)号：US11536758B2
公开(公告)日：2022-12-27
申请号：US16517046
申请日：2019-07-19
发明人： Jason L. Wardlaw , Michael A. Kost , Anthony S. Doy , Tejasvi Das , Siddharth Maru , Xin Zhao , Matthew Beardsworth , Bruce E. Duewer
摘要： A system may include an array of sensor elements, the array of sensor elements each comprising a first type of passive reactive element, a second type of passive reactive element electrically coupled to the array of sensor elements, a driver configured to drive the array of sensor elements and the second type of passive reactive element, and control circuitry configured to control enabling and disabling of individual sensor elements of the array of sensor elements to ensure no more than one of the array of sensor elements is enabled at a time such that when one of the array of sensor elements is enabled, the one of the array of sensor elements and the second type of passive reactive element together operate as a resonant sensor.
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公开(公告)号：US11536620B2
公开(公告)日：2022-12-27
申请号：US17011500
申请日：2020-09-03
发明人： Gavin McVeigh
摘要： Circuitry for biasing a sensor comprises a bias generator module configured to receive a supply voltage and to generate a bias voltage for biasing the sensor. The circuitry further comprises a control module configured to compare a voltage indicative of the supply voltage to a threshold voltage and to output a control signal to the bias generator module based on the comparison. The bias generator module is configured to control the bias voltage based on the control signal.
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公开(公告)号：US11528031B2
公开(公告)日：2022-12-13
申请号：US17184295
申请日：2021-02-24
摘要： This application relates to ADC circuitry. An ADC circuit (200) has first and second conversion paths (201a, 201b) for converting analogue signals to digital and is operable in first and second modes. In the first mode, the first and second conversion paths are connected to respective first and second input nodes (202a, 202b) to receive and convert full scale first and second analogue input signals (Ain1, Ain2) to separate digital outputs (Dout1, Dout2). In the second mode, the first and second conversion paths are both connected to the first input node (202a), to convert the first analogue input signal (Ain1) to respective first and second digital signals, and the first and second conversion paths are configured for processing different signal levels of the first analogue input signal. A selector (207) select the first digital signal or the second digital to be output as an output signal based on an indication of amplitude of the first analogue input signal.
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公开(公告)号：US11515707B2
公开(公告)日：2022-11-29
申请号：US17493129
申请日：2021-10-04
发明人： Graeme G. Mackay , Ajit Sharma , Jason W. Lawrence , Eric J. King
摘要： A power delivery system may include a power converter configured to electrically couple to a power source and further configured to supply electrical energy to one or more loads electrically coupled to an output of the power converter, and control circuitry configured to select a constraint factor from a plurality of different constraint factors based on at least one of an input voltage to the power converter and a power level available to the power converter, and control the power converter in accordance with the constraint factor.
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公开(公告)号：US11514951B2
公开(公告)日：2022-11-29
申请号：US17489187
申请日：2021-09-29
申请人： Dell Products L.P.
摘要： An information handling system may include a processor and a storage subsystem. The storage subsystem may include a non-expander backplane, a first plurality of storage resources coupled to the processor via the non-expander backplane, and a second plurality of storage resources coupled to the processor via a communication path that does not include the non-expander backplane. The information handling system may be configured to provide slot numbers for the storage resources according to a numbering scheme in which a storage resource from the first plurality of storage resources and a storage resource from the second plurality of storage resources have the same slot number.
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78.发明授权公开(公告)号：US11510340B2
公开(公告)日：2022-11-22
申请号：US16921304
申请日：2020-07-06
申请人： Dell Products L.P.
发明人： Steven Embleton , Travis C. North
摘要： A system may include a thermal source, a thermal sink, and heat-rejecting media comprising flexible graphite thermally coupled between the thermal source and the thermal sink and configured to transfer heat from the thermal source to the thermal sink.
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公开(公告)号：US11509272B2
公开(公告)日：2022-11-22
申请号：US17319620
申请日：2021-05-13
发明人： John P. Lesso , Toru Ido
摘要： This application describes time-encoding modulator circuitry (200), and in particular a PWM modulator suitable for use for a class-D amplifier. A forward signal path receives a digital input signal (Din) and outputs an output PWM signal (Sout) and includes a first PWM modulator (101). A feedback path provides feedback to an input of the first PWM modulator (101). The feedback path includes an ADC (203) which receive a first PWM signal (Sa) derived from the output PWM signal. The ADC (203) includes a second PWM modulator (401) which generates a second PWM signal (Sb) based on the first PWM signal. A controller (201) controls the second PWM modulator such that a PWM carrier of the second PWM signal is phase and frequency matched to a PWM carrier of the output PWM signal.
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公开(公告)号：US11500995B1
公开(公告)日：2022-11-15
申请号：US17240787
申请日：2021-04-26
申请人： Dell Products L.P.
IPC分类号： G06F9/44 , G06F21/57 , G06F9/4401
摘要： An information handling system may include at least one processor; and a computer-readable medium having instructions thereon that are executable by the at least one processor for: prior to initialization of an operating system, executing a pre-boot environment; and within the pre-boot environment, downloading a universal filesystem driver from a first back-end server and loading the universal filesystem driver in the pre-boot environment, wherein the universal filesystem driver is a single pre-boot firmware volume that comprises drivers for a plurality of different filesystems.
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