公开(公告)号：US3842414A

公开(公告)日：1974-10-15

申请号：US37100473

申请日：1973-06-18

申请人： IBM

发明人： CHEN T ,  HO I

IPC分类号： H03M7/12 ,  H03K13/24 ,  H04L3/00

CPC分类号： H03M7/12

摘要： Apparatus for encoding multi-digit binary-coded-decimal numbers of a predetermined quantity of bits, for example, of at least two decimal digits, into a re-expressed lower number of bits, the binary-coded-decimal number being expressed in the form (abcd) (efgh). An encoder selects a set from a class of sets of bit symbols with each set corresponding to a respective combination of the bits in the most significant position, (a) and (e), of each of the four-bit groups representing the respective digits of the binary-coded-decimal number to be encoded. The selected set is the set which corresponds to the respective combination and the encoder determines certain of the bits of the multi-digit binary-coded-decimal number to be encoded and leaves undetermined the remaining bits of the number. The encoder is connected to register means having a plurality of bit positions which are equal to the quantity of bits less than the predetermined quantity, and stores not only the determined bit symbols but also the undetermined other bits of the multi-digit binary-codeddecimal number.

摘要翻译： 用于将预定数量的位（例如至少两个十进制数字）的多位二进制编码十进制数编码为重新表示的较低位数的装置，二进制编码十进制数表示在 形式（abcd）（efgh）。 编码器从一组比特符号集合中选择一组，其中每个集合对应于表示相应数字的四比特组中的每一个的最高有效位置（a）和（e）中的比特的相应组合） 要编码的二进制编码十进制数。 所选集是对应于相应组合的集合，并且编码器确定要编码的多位二进制编码十进制数的某些位，并且不确定该数的剩余位。 编码器连接到具有等于小于预定量的位数的多个比特位置的寄存器装置，并且不仅存储所确定的比特符号，而且存储多位二进制编码的码元的未确定的其他比特， 十进制数。

公开(公告)号：US3748450A

公开(公告)日：1973-07-24

申请号：US3748450D

申请日：1971-10-18

申请人： COMTEC IND INC

发明人： FICO L ,  SHEKER R ,  BALLOU R ,  COSMAN D

IPC分类号： G06F15/02 ,  H03M7/12 ,  H03K13/24

CPC分类号： H03M7/12 ,  G06F15/0258

摘要： This translator is capable of receiving and automatically displaying most significant digit first, a number to any numerical base or radix; and it may then convert the number to another base and display the converted number, or it may store the number for use in an arithmetic operation. The translator keyboard includes a plurality of radix keys, and before a number is entered, its corresponding radix key is pushed to route the input data (number) to one of a plurality of holding registers, and simultaneously to a display register. When a number has been entered, it may be converted to another base and displayed, merely by pushing a different radix key. Alternatively the number can be stored by pushing a storage key, after which a second number is entered and an arithmetic unit may be operated to add, subtract, multiply or divide the two numbers.

摘要翻译： 该翻译器能够首先接收并自动显示最高有效数字，一个数字到任何数字基数或基数; 然后可以将该号码转换为另一个基座并显示转换的号码，或者可以存储用于算术运算的号码。 翻译键盘包括多个基数键，并且在输入数字之前，按下其对应的基数键将输入数据（数量）路由到多个保持寄存器之一，并同时显示给显示寄存器。 当输入了一个数字时，可以将其转换为另一个基数并显示，只需按一个不同的基数键即可。 或者，可以通过按下存储键来存储号码，之后输入第二号码，并且可以操作运算单元来加，减，乘或除两个号码。

公开(公告)号：US3731074A

公开(公告)日：1973-05-01

申请号：US3731074D

申请日：1971-03-12

申请人： DENKI ONKYO CO LTD

发明人： MASUDA N

IPC分类号： H03M7/04 ,  H03K17/90 ,  H03M7/08 ,  H03M7/12 ,  G06F5/02 ,  H03K13/24 ,  H03K13/247

CPC分类号： H03M7/12 ,  H03K17/90 ,  H03M7/08

摘要： A decimal-binary code conversion system wherein four amplifying circuits are formed by respectively connecting four magnetroresistance effect devices formed as a bridge circuit to each of four amplifiers which produce different output signals, four different numerical values being binary-coded with independent operation of four amplifying circuits, and six numerical values being binary-coded with composite operations of the two of four amplifying circuits.

摘要翻译： 一个十进制二进制代码转换系统，其中四个放大电路是通过将形成为桥接电路的四个磁阻效应器件分别连接到产生不同输出信号的四个放大器中的每一个形成的，四个不同的数值被二进制编码， 四个放大电路，六个数值由四个放大电路中的两个的复合操作进行二进制编码。

公开(公告)号：US3705299A

公开(公告)日：1972-12-05

申请号：US3705299D

申请日：1971-09-24

申请人： MESSERSCHMITT BOELKOW BLOHM

发明人： BASTIAN INGBERT ,  BROGL HORST

IPC分类号： H03M7/12 ,  G06F5/00

CPC分类号： H03M7/12

摘要： A circuit arrangement, for converting a decimal number expressed in the BCD code into a pure binary number, comprises plural binary full adder circuits arranged successively in ascending binary digit order and each having signal inputs and binary digit outputs. Plural BCD code input terminals have applied thereto the decimal number to be converted, and lines connect each code input terminal commonly to all those signal inputs of the adder circuits which are associated, in correct decimal column position, with those 2n numbers which yield, as their sum, the decimal number, expressed in the BCD code, and indicated, with consideration of its decimal column position, at their respective code input terminals. The adder circuits are interconnected in such a manner that the carryover and output signals of each binary full adder circuit are supplied in correct decimal column position to the signal inputs of the respective succeeding binary full adder circuit.

摘要翻译： 用于将以BCD码表示的十进制数转换为纯二进制数的电路装置包括以升序二进制数顺序连续布置的多个二进制全加器电路，每个具有信号输入和二进制数字输出。 将多个BCD码输入端子应用于要转换的十进制数，并且线路将每个代码输入端子共同连接到与正确的十进制列位置相关联的加法器电路的所有那些信号输入与产生的2n个数字，作为 它们的总和，十进制数，以BCD代码表示，并在考虑其十进制列位置的情况下在其各自的代码输入端子处指示。 加法器电路以这样的方式相互连接，使得每个二进制全加器电路的输入和输出信号以正确的十进制列位置提供给相应的后续二进制全加器电路的信号输入。

公开(公告)号：US3684878A

公开(公告)日：1972-08-15

申请号：US3684878D

申请日：1970-10-02

申请人： TELE CASH INC

发明人： SCHIPPER RICHARD A

IPC分类号： H03M7/12 ,  H03K13/258

CPC分类号： H03M7/12

摘要： A BCD to binary converter in which a plurality of shift registers receives BCD inputs in parallel and the outputs of each shift register is serially passed through 10-times multipliers until the proper decimal level is reached; each of the 10-times multipliers being an addition of a two-times and eight-times multiplier and the sum of the next least significant digit being added after each multiplication.

摘要翻译： 一个BCD到二进制转换器，其中多个移位寄存器并行地接收BCD输入，并且每个移位寄存器的输出串行地通过10倍乘法器，直到达到适当的小数级; 10倍乘法器中的每一个是两倍和八倍乘法器的相加，并且在每次乘法之后添加的下一个最低有效数字的和。

公开(公告)号：US3638002A

公开(公告)日：1972-01-25

申请号：US3638002D

申请日：1970-04-03

申请人： NASA

发明人： TOOLE PIERCE C

IPC分类号： H03M7/12 ,  H04L3/00

CPC分类号： H03M7/12

摘要： A high-speed binary-to-binary coded decimal converter which includes a plurality of decades connected in cascade. Interposed between each of said decades is a carry circuit. The carry circuit supplies carry numbers to the succeeding decade, plus it sends a corrector number back to a corrector circuit associated with the preceding decade. This corrector number is combined with binary numbers already stored in the corrector circuit to produce a proper signal on a readout device associated therewith.

摘要翻译： 一种高速二进制到二进制编码的十进制转换器，包括多级连接的几十年。 介于每十年之间的是一个进位电路。 进位电路在随后的十年中提供携带号码，再加上校正器号码返回到与前十年相关的校正器电路。 该校正器编号与已经存储在校正器电路中的二进制数进行组合，以在与其相关联的读出装置上产生适当的信号。

公开(公告)号：US3626167A

公开(公告)日：1971-12-07

申请号：US3626167D

申请日：1969-08-07

申请人： BURROUGHS CORP

发明人： GUCK LEROY R ,  HANSON LAWRENCE G ,  KNUTH DONALD E

IPC分类号： G06F9/30 ,  H03M7/12 ,  H04L3/00

CPC分类号： G06F9/30025 ,  H03M7/12

摘要： Data processing apparatus for shifting a binary signal coded in a first number base by digits coded in a second number base. A first register stores an operator identifying a shift. A second register stores a scale factor signal identifying the number of required digit shifts. Data processing apparatus is responsive to the stored shift operator and the stored scale factor for shifting the binary signal coded in the first number base by the number of digits in the second number base identified by the stored scale factor.

公开(公告)号：US3506815A

公开(公告)日：1970-04-14

申请号：US3506815D

申请日：1966-12-28

申请人： COLLINS RADIO CO

发明人： STONE JAMES S

IPC分类号： H03M7/12 ,  H03K13/00 ,  G06F5/02

CPC分类号： H03M7/12

公开(公告)号：US3500383A

公开(公告)日：1970-03-10

申请号：US3500383D

申请日：1966-10-31

申请人： SINGER GENERAL PRECISION

发明人： PROSS JOHN W JR

IPC分类号： H03M7/12 ,  G06F5/00

CPC分类号： H03M7/12

公开(公告)号：US3432811A

公开(公告)日：1969-03-11

申请号：US3432811D

申请日：1967-01-19

申请人： IBM

发明人： RINALDI RUSSELL G ,  MOORE BRIAN B

IPC分类号： G06F7/48 ,  G06F7/495 ,  G06F7/50 ,  G06F13/00 ,  H03M7/00 ,  H03M7/12 ,  H03M7/30 ,  G11B13/00

CPC分类号： G06F7/495 ,  G06F13/00 ,  G06F2207/3828 ,  H03M7/00 ,  H03M7/12 ,  H03M7/30