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1.发明授权
公开(公告)号：US3697733A
公开(公告)日：1972-10-10
申请号：US3697733D
申请日：1970-12-16
申请人： NASA
发明人： TOOLE PIERCE C
CPC分类号： G06F7/4915 , H03M7/12
摘要： A high speed apparatus for scaling and converting binary numbers of binary coded decimal numbers which includes a plurality of decades connected in cascade. A plurality of programmed boards are provided for receiving binary numbers of predetermined weights and scaling the numbers up a predetermined multiple thereof. Interposed between each of said decades is a carry circuit. A carry circuit supplies carry numbers to the succeeding decade, plus it sends a corrector number back to a corrector circuit associated with the preceding decade. This corrector number is combined with binary numbers already stored in the corrector circuit to produce a proper signal on a readout device associated therewith.
摘要翻译： 一种用于缩放和转换二进制编码十进制数的二进制数的高速装置，其包括级联连接的多个几十年。 多个编程板被提供用于接收预定权重的二进制数，并将数字缩放到其预定倍数。 介于每十年之间的是一个进位电路。 携带电路在随后的十年中提供携带号码，再加上校正器号码返回到与前十年相关的校正器电路。 该校正器编号与已经存储在校正器电路中的二进制编号组合，以在与其相关联的读出装置上产生适当的信号。
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公开(公告)号：US3638002A
公开(公告)日：1972-01-25
申请号：US3638002D
申请日：1970-04-03
申请人： NASA
发明人： TOOLE PIERCE C
CPC分类号： H03M7/12
摘要： A high-speed binary-to-binary coded decimal converter which includes a plurality of decades connected in cascade. Interposed between each of said decades is a carry circuit. The carry circuit supplies carry numbers to the succeeding decade, plus it sends a corrector number back to a corrector circuit associated with the preceding decade. This corrector number is combined with binary numbers already stored in the corrector circuit to produce a proper signal on a readout device associated therewith.
摘要翻译： 一种高速二进制到二进制编码的十进制转换器，包括多级连接的几十年。 介于每十年之间的是一个进位电路。 进位电路在随后的十年中提供携带号码，再加上校正器号码返回到与前十年相关的校正器电路。 该校正器编号与已经存储在校正器电路中的二进制数进行组合，以在与其相关联的读出装置上产生适当的信号。
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公开(公告)号：US3916084A
公开(公告)日：1975-10-28
申请号：US53653574
申请日：1974-12-26
申请人： NASA
发明人： TOOLE PIERCE C
CPC分类号： H04L7/033
摘要： An apparatus for extracting and generating a clock pulse train from a pulse coded data train. The apparatus includes a filter circuit for receiving the pulse coded data train. A first setreset flip-flop is provided for receiving the signals from the pulse coded train. Coupled to the output of the first flip-flop is a means for generating a triggering pulse responsive to the occurrence of data within the train. A pulse gate activated by said triggering pulse for causing the data from said pulse coded data train to be stored in a second flip-flop. A clock pulse generating means is coupled between the outputs of the first and second flip-flops for generating a continuous stream of clock pulses which are synchronized with the incoming pulse coded data train.
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