公开(公告)号：US09070794B2

公开(公告)日：2015-06-30

申请号：US14529092

申请日：2014-10-30

Applicant: Tsinghua University ,  Hon Hai Precision Industry Co., Ltd.

Inventor： Yang Wei ,  Shou-Shan Fan

IPC: H01L33/62 ,  H01L33/00 ,  H01L21/02 ,  H01L33/64 ,  H01L33/36 ,  H01L33/20 ,  B82Y10/00 ,  H01L51/00 ,  B82Y40/00

CPC classification number: H01L33/0062 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/20 ,  H01L33/36 ,  H01L33/64 ,  H01L33/641 ,  H01L51/0048 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

Abstract: A method for making light emitting diode, the method includes the following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. A first semiconductor layer, an active layer and a second semiconductor layer are grown on the epitaxial growth surface in that order. A third semiconductor layer is formed on a surface of the second semiconductor layer, wherein the third semiconductor layer includes a plurality of spaced protrusions. A portion of the first semiconductor layer is exposed by etching a portion of the third semiconductor layer, the second semiconductor layer, and the active layer. A first electrode is formed to electrically connected to the first semiconductor layer and a second electrode is formed to electrically connected to the second semiconductor layer.

Abstract translation: 一种制造发光二极管的方法，该方法包括以下步骤。 提供了具有外延生长面的基板。 碳纳米管层悬浮在外延生长表面上方。 在外延生长表面上依次生长第一半导体层，有源层和第二半导体层。 第三半导体层形成在第二半导体层的表面上，其中第三半导体层包括多个间隔开的突起。 通过蚀刻第三半导体层，第二半导体层和有源层的一部分来暴露第一半导体层的一部分。 第一电极被形成为电连接到第一半导体层，并且第二电极形成为电连接到第二半导体层。

公开(公告)号：US08951430B2

公开(公告)日：2015-02-10

申请号：US13833462

申请日：2013-03-15

Applicant: The Board of Trustees of the University of Illinois

Inventor： Xiuling Li ,  Matthew T. Dejarld ,  Jae Cheol Shin ,  Winston Chern

IPC: C03C15/00 ,  H01L21/306 ,  H01L33/00 ,  H01L31/18 ,  H01L33/20

CPC classification number: H01L21/30612 ,  H01L31/184 ,  H01L33/0062 ,  H01L33/20 ,  Y02E10/544 ,  Y02P70/521 ,  Y10S977/762

Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

Abstract translation: 提供金属辅助化学蚀刻III-V族半导体的方法。 所述方法可以包括提供设置在包括III-V半导体的半导体衬底上的导电膜图案。 通过将导电膜图案和半导体衬底浸入包含氧化电位小于氧化的酸和氧化剂的蚀刻剂溶液中，可以选择性地去除导电膜图案正下方的III-V半导体的至少一部分 过氧化氢的潜力。 这种方法可以形成高纵横比半导体纳米结构。

公开(公告)号：US08912079B2

公开(公告)日：2014-12-16

申请号：US13266337

申请日：2010-04-28

Applicant: Motoichi Ohtsu ,  Takashi Yatsui ,  Tadashi Kawazoe ,  Shunsuke Yamazaki ,  Koichi Kajiyama ,  Michinobu Mizumura ,  Keiichi Ito

Inventor： Motoichi Ohtsu ,  Takashi Yatsui ,  Tadashi Kawazoe ,  Shunsuke Yamazaki ,  Koichi Kajiyama ,  Michinobu Mizumura ,  Keiichi Ito

IPC: H01L21/20 ,  B05C9/08 ,  C23C16/48 ,  C23C16/30 ,  C30B25/00 ,  C30B29/40 ,  H01L21/02 ,  H01L33/00 ,  C23C14/54 ,  C23C16/52

CPC classification number: C23C16/481 ,  C23C14/548 ,  C23C16/303 ,  C23C16/52 ,  C30B25/00 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/0062

Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate. In the compound semiconductor deposition method of depositing a compound semiconductor of a ternary or higher system on a substrate, propagation light of a smaller energy than a desired ideal excitation energy for the compound semiconductor is irradiated onto the substrate 13 while depositing the compound semiconductor on the substrate 13, near-field light is generated based on the irradiated propagation light from fine particles of the compound semiconductor deposited on the substrate 13, new vibrational levels for the compound semiconductor are formed in multiple stages based on the generated near-field light, and a component in the compound semiconductor corresponding to the excitation energy is excited with the propagation light through a vibrational level, among the new vibrational levels, which has an excitation energy equal to or smaller than the energy of the propagation light is excited to desorb the component.

Abstract translation: 提供一种在将化合物半导体沉积在基板上时以纳米级调节三元或更高系统的化合物半导体的发光波长的化合物半导体沉积方法。 在将三元或更高系统的化合物半导体沉积在衬底上的化合物半导体沉积方法中，将化合物半导体所需的理想激发能的能量较小的传播光照射到衬底13上，同时将化合物半导体沉积在 基板13，基于沉积在基板13上的化合物半导体的微粒的照射的传播光产生近场光，基于产生的近场光，以多个阶段形成化合物半导体的新的振动电平，以及 对应于激发能的化合物半导体中的成分被传播光激发，通过振动水平，激发能量等于或小于传播光的能量的新的振动水平被激发，从而解吸部件 。

公开(公告)号：US08906726B2

公开(公告)日：2014-12-09

申请号：US13902958

申请日：2013-05-27

Applicant: Tsinghua University ,  Hon Hai Precision Industry Co., Ltd.

Inventor： Yang Wei ,  Shou-Shan Fan

IPC: H01L33/62

CPC classification number: H01L33/0062 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/20 ,  H01L33/36 ,  H01L33/64 ,  H01L33/641 ,  H01L51/0048 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

Abstract: A method for making light emitting diode, the method includes the following steps. First, a substrate having an epitaxial growth surface is provided. Second, a carbon nanotube layer is suspended above the epitaxial growth surface. Third, a first semiconductor layer, an active layer and a second semiconductor layer are grown on the epitaxial growth surface in that order, wherein the first semiconductor layer includes a buffer layer, an intrinsic semiconductor layer, and a doped semiconductor layer stacked in that order. Fourth, the doped semiconductor layer is exposed by removing the substrate, the buffer layer, and the intrinsic semiconductor layer. Fifth, a first electrode is prepared on the first semiconductor layer and a second electrode is prepared on the second semiconductor layer.

Abstract translation: 一种制造发光二极管的方法，该方法包括以下步骤。 首先，提供具有外延生长面的基板。 第二，碳纳米管层悬浮在外延生长表面上方。 第三，第一半导体层，有源层和第二半导体层以该顺序生长在外延生长表面上，其中第一半导体层包括缓冲层，本征半导体层和以该顺序堆叠的掺杂半导体层 。 第四，通过去除衬底，缓冲层和本征半导体层来暴露掺杂半导体层。 第五，在第一半导体层上制备第一电极，在第二半导体层上制备第二电极。

公开(公告)号：US08901534B2

公开(公告)日：2014-12-02

申请号：US13705792

申请日：2012-12-05

Applicant: GLO AB

Inventor： Patrik Svensson

IPC: H01L33/24 ,  H01L29/41 ,  H01L29/06 ,  H01L33/06 ,  H01L33/00 ,  H01L33/18 ,  H01L33/08

CPC classification number: H01L33/06 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/413 ,  H01L33/0062 ,  H01L33/08 ,  H01L33/18 ,  H01L33/24 ,  Y10S977/762

Abstract: A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids.

Abstract translation: 诸如LED的半导体器件包括位于支撑体上方的多个第一导电型半导体纳米线芯，在芯周围和周围延伸的连续的第二导电类型半导体层，位于第二导电类型半导体中的多个间隙 并且在芯之间延伸，以及与第二导电类型半导体层接触并延伸到间隙中的第一电极层。

公开(公告)号：US20140349427A1

公开(公告)日：2014-11-27

申请号：US14452346

申请日：2014-08-05

Applicant: Ostendo Technologies, Inc.

Inventor： Hussein S. El-Ghoroury ,  Benjamin A. Haskell

IPC: H01L33/00 ,  H01S5/026 ,  H01S5/30

CPC classification number: H01L33/0062 ,  H01L21/0242 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L27/156 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/08 ,  H01L33/16 ,  H01L2933/0025 ,  H01S5/026 ,  H01S5/3013

Abstract: Methods are described to utilize relatively low cost substrates and processing methods to achieve enhanced emissive imager pixel performance via selective epitaxial growth. An emissive imaging array is coupled with one or more patterned compound semiconductor light emitting structures grown on a second patterned and selectively grown compound semiconductor template article. The proper design and execution of the patterning and epitaxial growth steps, coupled with alignment of the epitaxial structures with the imaging array, results in enhanced performance of the emissive imager. The increased luminous flux achieved enables use of such images for high brightness display and illumination applications.

Abstract translation: 描述了利用相对低成本的衬底和处理方法来实现通过选择性外延生长来实现增强的发射成像器像素性能的方法。 发射成像阵列与在第二图案化和选择性生长的化合物半导体模板制品上生长的一个或多个图案化的化合物半导体发光结构耦合。 图案化和外延生长步骤的适当设计和执行以及外延结构与成像阵列的对准，导致发射成像器的性能提高。 所获得的增加的光通量使得能够使用这种图像用于高亮度显示和照明应用。

公开(公告)号：US20140326948A1

公开(公告)日：2014-11-06

申请号：US14348587

申请日：2012-08-22

Applicant: Ivar Tångring ,  Martin Rudolf Behringer

Inventor： Ivar Tångring ,  Martin Rudolf Behringer

IPC: H01L33/06 ,  H01L33/30 ,  H01L33/12 ,  H01L33/00

CPC classification number: H01L33/06 ,  B82Y20/00 ,  H01L33/0062 ,  H01L33/08 ,  H01L33/12 ,  H01L33/30 ,  H01L33/305 ,  H01S5/34326

Abstract: In at least one embodiment, the semiconductor layer sequence (1) is provided for an optoelectronic semiconductor chip (10). The semiconductor layer sequence (1) contains at least three quantum wells (2) which are arranged to generate electromagnetic radiation. Furthermore, the semiconductor layer sequence (1) includes a plurality of barrier layers (3), of which at least one barrier layer is arranged between two adjacent quantum wells (2) in each case. The quantum wells (2) have a first average indium content and the barrier layers (3) have a second, smaller, average indium content. A second average lattice constant of the barrier layers (3) is thereby smaller than a first average lattice constant of the quantum wells (2).

Abstract translation: 在至少一个实施例中，为光电半导体芯片（10）提供半导体层序列（1）。 半导体层序列（1）包含至少三个量子阱（2），其被布置成产生电磁辐射。 此外，半导体层序列（1）包括多个势垒层（3），其中在每种情况下在两个相邻的量子阱（2）之间布置有至少一个势垒层。 量子阱（2）具有第一平均铟含量，并且阻挡层（3）具有第二较小的平均铟含量。 因此阻挡层（3）的第二平均晶格常数小于量子阱（2）的第一平均晶格常数。

公开(公告)号：US20140211820A1

公开(公告)日：2014-07-31

申请号：US14229674

申请日：2014-03-28

Applicant: The Regents of the University of California

Inventor： Robert M. Farrell, JR. ,  Troy J. Baker ,  Arpan Chakraborty ,  Benjamin A. Haskell ,  P. Morgan Pattison ,  Rajat Sharma ,  Umesh K. Mishra ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

IPC: H01S5/343

CPC classification number: H01L33/16 ,  B82Y20/00 ,  C30B23/025 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L33/0004 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/02 ,  H01S5/0422 ,  H01S5/2201 ,  H01S5/3202 ,  H01S5/34333 ,  H01S2304/04

Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.

Abstract translation: 一种用于生长和制造半极性（Ga，Al，In，B）N薄膜，异质结构和器件的方法，包括鉴定特定器件应用的所需材料性质，基于所需材料性质选择半极性生长取向，选择 用于生长选择的半极性生长取向的合适底物，在衬底上生长平面半极性（Ga，Al，In，B）N模板或成核层，以及生长半极（Ga，Al，In，B）N薄膜 ，平面半极性（Ga，Al，In，B）N模板或成核层上的异质结构或器件。 该方法导致大面积的半极性（Ga，Al，In，B）N薄膜，异质结构和器件平行于衬底表面。

公开(公告)号：US08790999B2

公开(公告)日：2014-07-29

申请号：US13775794

申请日：2013-02-25

Applicant: Kabushiki Kaisha Toshiba

Inventor： Naoharu Sugiyama ,  Tomonari Shioda ,  Shinya Nunoue

IPC: H01L21/36 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L21/36 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/7624 ,  H01L21/76243 ,  H01L29/2003 ,  H01L29/7787 ,  H01L33/0062

Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness.

Abstract translation: 根据一个实施例，公开了一种用于制造氮化物半导体晶体层的方法。 该方法可以包括在硅晶体层上形成具有第一厚度的氮化物半导体晶体层。 硅晶层设置在基体上。 硅晶层在形成氮化物半导体晶体层之前具有第二厚度。 第二厚度比第一厚度薄。 形成氮化物半导体晶体层包括使至少部分掺入氮化物半导体晶体层中的硅晶体层从第二厚度减小硅晶体层的厚度。

公开(公告)号：US20130288412A1

公开(公告)日：2013-10-31

申请号：US13908902

申请日：2013-06-03

Applicant: Liang WANG ,  Ilyas MOHAMMED ,  Masud BEROZ

Inventor： Liang WANG ,  Ilyas MOHAMMED ,  Masud BEROZ

IPC: H01L33/00

CPC classification number: H01L23/562 ,  H01L21/02002 ,  H01L21/02035 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02414 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L27/0207 ,  H01L33/005 ,  H01L33/0062 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00

Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.