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    Simultaneous function dynamic random access memory device technique
    62.
    发明授权
    Simultaneous function dynamic random access memory device technique 有权
    同步功能动态随机存取存储器件技术

    公开(公告)号：US06643212B1

    公开(公告)日：2003-11-04

    申请号：US10125758

    申请日：2002-04-18

    申请人： Oscar Frederick Jones, Jr. ,  Michael C. Parris

    发明人： Oscar Frederick Jones, Jr. ,  Michael C. Parris

    IPC分类号： G11C800

    CPC分类号： G11C7/22 ,  G11C7/1042 ,  G11C2207/104 ,  G11C2207/108 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.

    摘要翻译： 特别适用于DRAM，同步DRAM（“SDRAM”），专用DRAM，嵌入式DRAM，嵌入式SDRAM等的同时功能动态随机存取存储器（“DRAM”）技术，其能够执行“读取”，“写入” ，“活动”和“预充电”命令。 本发明的技术特别适用于嵌入式存储器阵列或特殊DRAM，其中DRAM的输入信号的数量不一定受到机械部件封装约束或分量引脚计数的限制。 一般来说，该技术的优点是通过使用单独的地址字段（包括用于“读取”和“写入”命令的存储区地址）来获得，并且通过使用高度并行的“高效”命令来分离“活动”和“预充电”命令的存储体地址 操作功能。

    Semiconductor memory device with internal data reading timing set precisely
    63.
    发明申请
    Semiconductor memory device with internal data reading timing set precisely 失效
    具有内部数据读取定时精度的半导体存储器件

    公开(公告)号：US20030202412A1

    公开(公告)日：2003-10-30

    申请号：US10329355

    申请日：2002-12-27

    申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

    发明人： Koji Nii ,  Yasunobu Nakase

    IPC分类号： G11C007/14

    CPC分类号： G11C7/227 ,  G11C7/22 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/24 ,  G11C2207/2281 ,  G11C2207/229

    摘要： Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

    摘要翻译： 每个具有与正常存储器单元相同布局的虚拟单元在行方向上与正常存储器单元对齐，并且被排列成行和列。 在每个虚拟单元列中，布置虚拟位线，并且当选择一个字线时，多个虚拟单元同时选择并连接到相应的虚拟位线。 电压检测电路检测虚拟位线上的电位以确定读出放大器的激活时序。 在半导体存储器件中，可以高速地改变虚拟位线上的电位，并且能够独立于存储单元阵列的结构来优化内部数据读取定时。

    Semiconductor memory device
    64.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06615309B2

    公开(公告)日：2003-09-02

    申请号：US10337977

    申请日：2003-01-08

    申请人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

    发明人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

    IPC分类号： G06F1202

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

    摘要翻译： 半导体存储器件。 该设备包括位线，耦合到位线的存储单元，耦合到存储单元的字线。 为了从存储单元读取数据和读取操作的开始，读取操作的读取命令的第一次与在写入操作的写入命令的接收之间的第二时间不同，以便写入 数据到存储单元和写入操作的开始。

    Method and apparatus for reducing the number of programmed bits in a memory array
    65.
    发明授权
    Method and apparatus for reducing the number of programmed bits in a memory array 有权
    用于减少存储器阵列中的编程位数的方法和装置

    公开(公告)号：US06611456B2

    公开(公告)日：2003-08-26

    申请号：US09898725

    申请日：2001-07-03

    申请人： Alexander Kushnarenko

    发明人： Alexander Kushnarenko

    IPC分类号： G11C1604

    CPC分类号： G11C16/26 ,  G11C7/22 ,  G11C16/10 ,  G11C2207/229

    摘要： A memory system that reduces the number of memory cells programmed in a memory array is provided. A logic comparator determines whether more than half of the bits of a write data word require a program operation. If so, the logic comparator provides a status signal having a first state. A status signal having the first state causes the inverse of the write data word to be written to the memory array, along with the status signal. If the status signal does not have the first state, the write data word is written to the memory array, along with the status signal. During a read operation, a data word and corresponding status signal are read from the array. If the status signal has the first state, the inverse of the data word is provided as a read data word. Otherwise, the data word is provided as the read data word.

    摘要翻译： 提供了减少存储器阵列中编程的存储器单元的数量的存储器系统。 逻辑比较器确定写入数据字的多于一半的位是否需要编程操作。 如果是，则逻辑比较器提供具有第一状态的状态信号。 具有第一状态的状态信号使得将写入数据字的反相与状态信号一起写入存储器阵列。 如果状态信号不具有第一状态，写数据字与状态信号一起写入存储器阵列。 在读取操作期间，从阵列读取数据字和对应的状态信号。 如果状态信号具有第一状态，则数据字的反向被提供为读取数据字。 否则，数据字被提供为读取数据字。

    Block write circuit and method for wide data path memory device
    67.
    再颁专利
    Block write circuit and method for wide data path memory device 有权
    块写电路和方法用于宽数据路径存储器件

    公开(公告)号：USRE38109E1

    公开(公告)日：2003-05-06

    申请号：US10029572

    申请日：2001-12-20

    申请人： Todd A. Merritt ,  Layne Bunker

    发明人： Todd A. Merritt ,  Layne Bunker

    IPC分类号： G11C700

    CPC分类号： G11C7/1048 ,  G11C7/1006 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/104 ,  G11C2207/108 ,  G11C2207/229

    摘要： A block write circuit in a memory device having a wide internal data path performs block write and data masking functions. The memory device includes a plurality of data terminals adapted to receive respective data signals, and a plurality of array groups each including a plurality of arrays and each array includes a plurality of memory cells. A plurality of input/output line groups each include a plurality of input/output lines coupled to the arrays of an associated array group. The block write circuit comprises a plurality of write driver groups, each write driver group including a plurality of write driver circuits having outputs coupled to respective data lines in an associated data line group. Each write driver circuit includes an input and develops a data signal on its output responsive to a data signal applied on its input. A multiplexer circuit includes a plurality of inputs coupled to respective data terminals, and a plurality of output subgroups. Each output subgroup is associated with a respective input, and each output group includes a plurality of outputs coupled to the write driver circuits in an associated write driver group. The multiplexer circuit operates responsive to a control in a block write mode to couple each of its inputs to the outputs in the associated output subgroup. A masking circuit may also mask data from respective input/output lines responsive to masking signals.

    摘要翻译： 具有宽内部数据路径的存储器件中的块写入电路执行块写入和数据屏蔽功能。 存储器件包括适于接收相应数据信号的多个数据端子，以及多个阵列组，每个阵列组包括多个阵列，每个阵列包括多个存储器单元。 多个输入/输出线组各自包括耦合到相关阵列组的阵列的多个输入/输出线。 块写入电路包括多个写入驱动器组，每个写入驱动器组包括具有耦合到相关联的数据线组中的相应数据线的输出的多个写入驱动器电路。 每个写入驱动器电路包括输入，并响应于在其输入上施加的数据信号在其输出上产生数据信号。 多路复用器电路包括耦合到相应数据终端的多个输入和多个输出子组。 每个输出子组与相应的输入相关联，并且每个输出组包括耦合到相关写入驱动器组中的写入驱动器电路的多个输出。 复用器电路响应于块写入模式中的控制而操作，以将其输入中的每一个耦合到相关输出子组中的输出。 屏蔽电路还可以响应于屏蔽信号来掩蔽相应输入/输出线路的数据。

    Rambus dynamic random access memory
    69.
    发明申请
    Rambus dynamic random access memory 失效
    Rambus动态随机存取存储器

    公开(公告)号：US20030056056A1

    公开(公告)日：2003-03-20

    申请号：US10238186

    申请日：2002-09-10

    发明人： Nak Kyu Park

    IPC分类号： G06F012/00

    CPC分类号： G11C7/1087 ,  G06F13/1647 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C2207/229 ,  Y02D10/14

    摘要： Disclosed is a Rambus DRAM capable of reducing power consumption and layout area by enabling data read/write control signal of accessed memory bank only, in a top memory bank and a bottom memory bank. The disclosed comprises: a top and a bottom memory bank blocks including a plurality of unit memory banks, respectively; and a data read/write control signal generation block for generating a top data write control signal and a top data read control signal to the top memory bank block and a bottom data write control signal and a bottom data read control signal to the bottom memory bank block, thereby controlling the top memory bank block and the bottom memory bank block to separately operate in data read/write operations.

    摘要翻译： 公开了一种Rambus DRAM，其能够通过仅在顶部存储体和底部存储体中实现访问存储体的数据读/写控制信号来降低功耗和布局面积。 所公开的包括：分别包括多个单元存储体的顶部和底部存储体块; 以及数据读/写控制信号产生块，用于产生顶部存储体块的顶部数据写入控制信号和顶部数据读取控制信号，并将底部数据写入控制信号和底部数据读取控制信号发送到底部存储体 从而控制顶部存储体块和底部存储体块以在数据读/写操作中单独操作。