公开(公告)号：US20040128468A1

公开(公告)日：2004-07-01

申请号：US10734624

申请日：2003-12-15

申请人： Hewlett-Packard Development Company, L.C.

发明人： Kevin Lloyd-Jones

IPC分类号： G06F009/26

CPC分类号： G06F12/0238 ,  G06F12/0292 ,  G06F2212/2024 ,  G06F2212/7201

摘要： There is disclosed a method and apparatus for mapping between logical and physical addresses in a solid state data storage device, particularly but not exclusively a magnetic random access solid state data storage device, in which a list of mappings between ranges of logical addresses and ranges of physical addresses are stored in a data table, the mappings being operated on to look up a physical address from a logical address and vice versa, and being operated on by a data processor, to amend the data mappings by introduction of new ranges of logical and physical addresses, upon ranges of individual physical memory elements becoming defective.

摘要翻译： 公开了一种用于在固态数据存储装置中的逻辑地址和物理地址之间进行映射的方法和装置，特别地但不排他地是磁随机存取固态数据存储装置，其中逻辑地址和范围的范围之间的映射列表 物理地址存储在数据表中，操作映射以从逻辑地址查找物理地址，反之亦然，并由数据处理器进行操作，以通过引入新的逻辑和逻辑范围来修改数据映射， 物理地址，各个物理存储器元件的范围变得有缺陷。

公开(公告)号：US20030131211A1

公开(公告)日：2003-07-10

申请号：US10325250

申请日：2002-12-19

发明人： Maksim Kuzmenka ,  Siva Raghuram Chennupati

IPC分类号： G06F009/26

CPC分类号： G06F9/30141 ,  G06F13/4086

摘要： A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

摘要翻译： 存储器寄存器和多个存储器单元之间的分支命令/地址总线结构包括连接到存储器寄存器的主总线。 第一子总线连接到主总线并分支成第一数量的存储单元总线，其中每个总线连接到与其相关联的存储器单元的命令/地址输入。 第二子总线也连接到主总线并分支成第二数量的存储单元总线，其中每个存储单元总线连接到与其相关联的存储器单元的命令/地址输入，其中第二数量较小 比第一个数字。 此外，第二子总线分支成多个辅助总线，其中辅助总线的数量对应于第一数量和第二数量之间的差异，其中每个辅助总线对应于存储器单元总线被电容性加载，并且不 用于驱动存储单元。

公开(公告)号：US20030056078A1

公开(公告)日：2003-03-20

申请号：US10169064

申请日：2002-10-23

发明人： Nicklas Johansson ,  Lichun Chen

IPC分类号： G06F009/26

CPC分类号： H01L27/12 ,  B82Y10/00 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/60 ,  H01L51/0037

摘要： A ferroelectric memory circuit (C) comprises a ferroelectric memory cell in the form of a ferroelectric polymer thin film (F) and first and second electrodes (E1; E2) respectively, contacting the ferroelectric memory cell (F) at opposite surfaces thereof, whereby a polarization state of the cell can be set, switched or detected by applying appropriate voltages to the electrodes (E1; E2). At least one of the electrodes (E1; E2) comprises at least one contact layer (P1; P2), said at least one contact layer (P1; P2) comprising a conducting polymer contacting the memory cell (C), and optionally a second layer (M1; M2) of a metal film contacting the conducting polymer (P1; P2), whereby said at least one of the electrodes (E1; E2) either comprises a conducting polymer contact layer (P1; P2) only, or a combination of a conducting polymer contact layer (P1; P2) and a metal film layer (M1; M2). A method in the fabrication of a ferroelectric memory circuit of this kind comprises steps for depositing a first contact layer of conducting polymer thin film on the substrate, depositing subsequently a ferroelectric polymer thin film on the first contact layer, and then depositing a second contact layer on the top of the ferroelectric polymer thin film.

摘要翻译： 铁电存储器电路（C）分别包括铁电聚合物薄膜（F）和第一和第二电极（E1; E2）形式的强电介质存储单元，所述铁电存储单元在其相对表面处与铁电存储单元（F）接触，由此 可以通过向电极（E1; E2）施加适当的电压来设置，切换或检测电池的极化状态。 电极（E1; E2）中的至少一个包括至少一个接触层（P1; P2），所述至少一个接触层（P1; P2）包括接触存储器单元（C）的导电聚合物， 与所述导电聚合物（P1; P2）接触的金属膜的层（M1; M2），其中所述至少一个所述电极（E1; E2）仅包括导电聚合物接触层（P1; P2） 的导电聚合物接触层（P1; P2）和金属膜层（M1; M2）。 制造这种铁电存储器电路的方法包括以下步骤：在衬底上沉积导电聚合物薄膜的第一接触层，然后在第一接触层上沉积铁电聚合物薄膜，然后沉积第二接触层 在铁电聚合物薄膜的顶部。

公开(公告)号：US20040148487A1

公开(公告)日：2004-07-29

申请号：US10707941

申请日：2004-01-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Masaya Mori ,  Shinpei Watanabe ,  Yoshihisa Takatsu ,  Toshio Sunaga

IPC分类号： G06F007/00 ,  G06F017/00 ,  G06F009/26 ,  G06F009/34 ,  G06F012/00

CPC分类号： G06F17/30949 ,  H04L29/12839 ,  H04L61/6022

摘要： Upon implementing a data registration into or a data retrieval from a data table (3) where first item data are registered along with corresponding second item data, there are used a first pointer table (1) where pointers to part of the registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a first hash function (6) to the first item data of the part of the registered data, and a second pointer table (2) where pointers to the other registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a second hash function (22) to the first item data of the other registered data.

公开(公告)号：US20040093475A1

公开(公告)日：2004-05-13

申请号：US10659563

申请日：2003-09-10

发明人： Wan-Hee Jo

IPC分类号： G06F009/26

CPC分类号： G06T3/40

摘要： The present disclosure relates to an address sub-sampling apparatus and method, and an image sensor employing the same. An address sub-sampling apparatus includes a counting unit that generates a binary address of N bits, N being a natural number larger than 2. The address sub-sampling apparatus also includes an address conversion unit that sub-samples the binary address of N bits to output a sub-sampled address having first, second and third bit groups, wherein the sub-sampled address is arranged in order of the third, the first and the second bit groups from the MSB (Most Significant Bit). The first bit group, which is a combination of digits in the sub-sampled address corresponding to the number of addresses to be skipped, being set as null0null, the second bit group, which includes the LSB (Least Significant Bit) corresponding to bits of the binary address, and the third bit group, which includes the MSB being set to shift address subtracted by the number of bits in the first bit group from the MSB in the binary address.

摘要翻译： 本公开涉及地址子采样装置和方法，以及采用该方法的图像传感器。 地址子采样装置包括：计数单元，其产生N比特的二进制地址，N是大于2的自然数。地址子采样装置还包括地址转换单元，对N比特的二进制地址进行子采样 以输出具有第一，第二和第三位组的子采样地址，其中子采样地址按照第三位，第一位和第二位组从MSB（最高有效位）排列。 作为与要跳过的地址数相对应的子采样地址中的数字的组合的第一位组被设置为“0”，第二位组包括对应于的LSB（最低有效位） 二进制地址的位和第三位组，其包括将MSB设置为移位地址，从第二位组中的位数减去二进制地址中的MSB。

公开(公告)号：US20030182531A1

公开(公告)日：2003-09-25

申请号：US10101399

申请日：2002-03-19

发明人： Esin Terzioglu ,  Gil I. Winograd

IPC分类号： G06F009/26

CPC分类号： G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

摘要： The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

公开(公告)号：US20030105936A1

公开(公告)日：2003-06-05

申请号：US09998920

申请日：2001-11-30

发明人： Christopher J. Stakutis ,  Christopher Whalley

IPC分类号： G06F009/26

CPC分类号： G06F3/0601 ,  G06F2003/0697

摘要： The invention provides an improved digital data processing system, e.g., storage area network (SAN), of the type having a first digital data processor, e.g., a SAN server, and a second digital data processor, e.g., a SAN client, coupled to one another and to one or more storage units, e.g., disk drives. A volume is stored on one or more of the storage devices, with at least two of its blocks residing at locations that are not contiguous with one another. The improvement is characterized, according to aspects of the invention, by transmission from the first to the second digital data processor of one or more addresses. These can constitute, in total, fewer such addresses than would be provided in a canonical map of the volume and, indeed, can comprise (by way of non-limiting example) a start address for each file and/or a portion of the volume on each storage device where the volume resides. The improvement is further characterized by an interpreter on the second digital data processor that interprets intermediate code (e.g., p-code) or other software to determine physical locations of the blocks that comprise the volume and/or file as a function of the addresses received from the first digital data processor. That software, according to aspects of the invention, embodies a methodology for determining the physical block addresses of a volume and/or file, e.g., from the volume start address(es). It can, according to further aspects of the invention, be transmitted by the first digital data processor to the second digital data processor, though it can be sourced from elsewhere, as well.

摘要翻译： 本发明提供了一种改进的数字数据处理系统，例如，存储区域网络（SAN），其具有第一数字数据处理器（例如，SAN服务器）和第二数字数据处理器（例如，SAN客户机），耦合到 一个或多个存储单元，例如磁盘驱动器。 卷存储在一个或多个存储设备上，其中至少两个块驻留在彼此不连续的位置。 根据本发明的方面，通过从第一数字数据处理器到第二数字数据处理器的一个或多个地址的传输来表征改进。 这些可以总共构成比体积的规范映射中提供的这样的地址更少，并且实际上可以包括（作为非限制性示例）每个文件的起始地址和/或卷的一部分 在卷所在的每个存储设备上。 该改进的特征还在于第二数字数据处理器上的解释器解释中间代码（例如，p代码）或其他软件，以确定构成该卷和/或文件的块的物理位置作为接收的地址的函数 从第一个数字数据处理器。 根据本发明的方面，该软件体现了用于例如从卷开始地址确定卷和/或文件的物理块地址的方法。 根据本发明的另一方面，可以通过第一数字数据处理器将其发送到第二数字数据处理器，尽管它也可以来自其他地方。

公开(公告)号：US20030056077A1

公开(公告)日：2003-03-20

申请号：US10079507

申请日：2002-02-22

发明人： Hirofumi Muramatsu

IPC分类号： G06F009/26 ,  G06F012/00

CPC分类号： G11C8/10 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096

摘要： A micro-controller is connected to an external circuit via an address bus and a read control signal line. The external circuit includes an enable circuit, a decoder and a register group. The enable circuit produces an enable signal from the sixteenth bit of 16-bit information on the address bus and a control signal on the read control signal line. The decoder creates an address from the ninth to fifteenth bits of the 16-bit information. When the enable signal is valid, the register group writes a signal value of the first to eighth bits of the 16-bit information into a register specified by the address. Accordingly, the micro-controller can send the read control signal, the register address and the register data to the external circuit via the address bus. It is therefore possible to write data into the external circuit without using a write control signal line.

摘要翻译： 微控制器通过地址总线和读控制信号线连接到外部电路。 外部电路包括使能电路，解码器和寄存器组。 使能电路从地址总线上的16位信息的第16位和读取控制信号线上的控制信号产生使能信号。 解码器从16位信息的第9位到第15位创建一个地址。 当使能信号有效时，寄存器组将16位信息的第1位到第8位的信号值写入地址指定的寄存器中。 因此，微控制器可以通过地址总线将读控制信号，寄存器地址和寄存器数据发送到外部电路。 因此，可以在不使用写入控制信号线的情况下将数据写入外部电路。

公开(公告)号：US20030037220A1

公开(公告)日：2003-02-20

申请号：US09930625

申请日：2001-08-15

申请人： Transmeta Corporation

发明人： H. Peter Anvin ,  Alex Klaiber ,  Guillermo J. Rozas ,  Parag Gupta

IPC分类号： G06F009/26

CPC分类号： G06F9/355 ,  G06F9/30101

摘要： A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.

摘要翻译： 一种用于将复杂X86分段操作和分段寻址分解为显式子操作的方法和装置，以便将它们暴露于基于编译器或基于翻译器的优化。

公开(公告)号：US20020138799A1

公开(公告)日：2002-09-26

申请号：US10154210

申请日：2002-05-23

发明人： Katsuhiko Takano

IPC分类号： G11C029/00 ,  G06F009/26 ,  G06F009/34 ,  G06F012/00 ,  G06F012/02 ,  G06F012/04 ,  G06F012/08 ,  G06F012/10

CPC分类号： G11C29/56

摘要： A memory device testing apparatus transfers at high speed a fail signal from a failure analysis memory unit 100 to a memory failure remedy analysis unit 200. The failure analysis memory unit 100 has a data storage memory 110 and a compact memory 120. The data storage memory 110 is divided into at least two sub address spaces. The divided sub address spaces are assigned to the addresses in the compact memory 120. A address generation control unit reads data stored in the compact memory 120. An address generation unit 132 generates a memory address signal 143 based on a sub address signal 141 and a detail address signal 142. The detail address signal 142 is incremented by the address generation control unit 125. The data in the sub address space storing the fail signal is transferred to the memory failure remedy analysis unit 200. If the data read from the compact memory 120 does not contain failure information, the data stored in the corresponding sub address space is not transferred.

摘要翻译： 存储器件测试装置将故障分析存储器单元100的故障信号高速地传送到存储器故障补救分析单元200.故障分析存储单元100具有数据存储存储器110和紧凑型存储器120.数据存储存储器 110被划分为至少两个子地址空间。 划分的子地址空间被分配给紧凑型存储器120中的地址。地址生成控制单元读取存储在紧凑型存储器120中的数据。地址生成单元132基于子地址信号141生成存储器地址信号143， 详细地址信号142由地址产生控制单元125递增。存储故障信号的子地址空间中的数据被传送到存储器故障补救分析单元200.如果从紧凑型存储器读取的数据 120不包含故障信息，存储在相应子地址空间中的数据不传输。