公开(公告)号：US20020078318A1

公开(公告)日：2002-06-20

申请号：US09738581

申请日：2000-12-18

申请人： International Business Machines Corporation

发明人： Freeman Leigh Rawson III

IPC分类号： G06F015/177 ,  G06F012/02 ,  G06F009/34

CPC分类号： H04L41/046 ,  H04L49/90 ,  H04L67/125 ,  H04L67/34

摘要： Disclosed is a server farm or MetaServer environment in which thin servers or server appliances each include a programmable network interface card providing logic required for implementing service processor functions. The combined implementation of the network interface and service processor hardware and software substantially eliminates redundancies, which previously existed when both were separate components. Service processor functions that are provided on the programmable network interface card includes gathering sensor data about the hardware, forwarding alerts regarding hardware state, initiating shutdown and restart on command, and responding to operating system service processor inquiries and commands. Additionally, other low-level management and control functions are provided on the programmable network interface card. Also, in one embodiment, a re-partitioning of the functions between the service processor (or probes) and the network interface is provided.

摘要翻译： 公开了一种服务器场或MetaServer环境，其中瘦服务器或服务器设备各自包括提供执行服务处理器功能所需的逻辑的可编程网络接口卡。 网络接口和服务处理器硬件和软件的组合实现基本上消除了当两者都是单独组件时先前存在的冗余。 在可编程网络接口卡上提供的服务处理器功能包括收集关于硬件的传感器数据，转发有关硬件状态的警报，启动关机和重新启动命令，以及响应操作系统服务处理器的查询和命令。 此外，可编程网络接口卡上还提供了其他低级管理和控制功能。 此外，在一个实施例中，提供了服务处理器（或探针）和网络接口之间的功能的重新分区。

公开(公告)号：US20020016865A1

公开(公告)日：2002-02-07

申请号：US09828120

申请日：2001-04-09

发明人： Hiroyuki Yanagi ,  Shinji Nakagawa ,  Motoyuki Katoh ,  Yosuke Baba

IPC分类号： G06F009/44 ,  G06F012/00 ,  G06F009/26 ,  G06F009/34 ,  G06F012/02 ,  G06F012/04 ,  G06F012/08 ,  G06F012/10

CPC分类号： G06F9/449 ,  Y10S707/99944

摘要： Relating to a method succeeded among a plurality of classes having a hierarchical relationship and the method overwriting the succeeded method, a method table stores therein method information including starting addresses of the storage locations of the respective methods, in which the respective method information is connected in series along the hierarchical relationship between the position classes of the respective methods. When a storage location of a message called by the message of a method call is retrieved, the retrieval of the method table is executed by the key which is the class designated by the message. Unless any designated method is retrieved by this retrieval, the key which is a super class of the designated class executes the retrieval based on the class table.

摘要翻译： 关于在具有层次关系的多个类中成功的方法和覆盖成功方法的方法，方法表存储方法信息，其中包括各方法信息所连接的各方法的存储位置的起始地址 沿着各个方法的位置类之间的层次关系。 当检索到通过方法调用的消息调用的消息的存储位置时，方法表的检索由作为消息指定的类的密钥执行。 除非通过此检索检索到任何指定的方法，否则作为指定类的超类的密钥将基于类表执行检索。

公开(公告)号：US20040098559A1

公开(公告)日：2004-05-20

申请号：US10700573

申请日：2003-11-05

申请人： Renesas Technology Corp.

发明人： Norio Masui

IPC分类号： G06F012/10 ,  G06F012/08 ,  G06F012/04 ,  G06F012/02 ,  G06F012/00 ,  G06F009/34 ,  G06F009/26

CPC分类号： G06F12/1036 ,  G06F2212/1028 ,  Y02D10/13

摘要： Provided is a TLB that can translate rapidly a virtual address to a physical address at small power consumption. A tag entry part (808) includes an ASID hold part (810), virtual address hold part (811), valid bit part (812), ASID comparison judgment part (102), and a virtual address comparison judgment part (104). By an ASID match line (105), a plurality of CAM cells (813) of the ASID hold part (810) are connected in parallel to each other and also connected to the ASID comparison judgment part (102). By a virtual address match line (106), a plurality of CAM cells (813) of the virtual address hold part (811) are connected in parallel to each other and also connected to the virtual address comparison judgment part (104). An ASID effective signal (107) is provided from the ASID comparison judgment part (102) to the virtual address comparison judgment part (104).

摘要翻译： 提供了一种TLB，可以以较小的功耗快速将虚拟地址转换为物理地址。 标签输入部分（808）包括ASID保持部分（810），虚拟地址保持部分（811），有效位部分（812），ASID比较判断部分（102）和虚拟地址比较判断部分（104）。 通过ASID匹配线（105），ASID保持部分（810）的多个CAM单元（813）彼此并联连接，并且还连接到ASID比较判断部分（102）。 通过虚拟地址匹配线（106），虚拟地址保持部分（811）的多个CAM单元（813）彼此并联连接，并且还连接到虚拟地址比较判断部分（104）。 从ASID比较判断部（102）向虚拟地址比较判定部（104）提供ASID有效信号（107）。

公开(公告)号：US20020075587A1

公开(公告)日：2002-06-20

申请号：US10075696

申请日：2002-02-14

申请人： SONY CORPORATION

发明人： Nobuhiro Tsurumaki ,  Keiji Tadokoro ,  Masato Yokota ,  Toru Yumine

IPC分类号： G06F012/00 ,  G11B015/18 ,  G11B017/00 ,  G11B019/02 ,  G06F012/14 ,  G06F012/16 ,  G06F013/00 ,  G06F013/28 ,  G06F009/26 ,  G06F009/34 ,  G06F012/02 ,  G06F012/04 ,  G06F012/08 ,  G06F012/10

CPC分类号： G06F3/0607 ,  G06F3/0601 ,  G06F3/0634 ,  G06F3/0686 ,  G06F2003/0697 ,  G11B5/41 ,  G11B15/6835 ,  G11B17/225 ,  G11B17/228 ,  G11B27/002 ,  G11B27/36 ,  G11B2220/41 ,  G11B2220/90

摘要： A cassette library (1) is provided with a driving apparatus (13), cassette housing shelves (14, 15) and a cassette carrier (16). A library controller (2) simulates as if driving apparatuses (13) having continuous address numbers were apparently used in the host computer (3) even when physically discontinuous address numbers are allocated to the driving apparatus (13), thereby making it possible to set occupancy for a driving apparatus with an arbitrary address number. The library controller (2) has the cassette carrier (16) automatically carry, at a preset timing, a cleaning cassette from the cassette housing shelf (14, 15) to the driving apparatus (13) to clean a recording reproduction head of the driving apparatus (13) using the cleaning cassette which is then carried back to the housing section in the original cassette housing shelf (14, 15) after the cleaning work.

摘要翻译： 盒式存储器（1）设有驱动装置（13），盒式磁带架（14,15）和盒式磁带架（16）。 图书馆控制器（2）模拟仿佛即使在物理上不连续的地址号被分配给驱动装置（13）的情况下，具有连续的地址号码的驱动装置（13）在主计算机（3）中被明显地使用，从而使得可以设置 占用具有任意地址号的驱动装置。 磁带库控制器（2）具有盒式磁带托架（16），在预先设定的时间自动将清洁盒带从磁带盒架（14,15）驱动到驱动设备（13），以清洁驾驶的记录再现磁头 装置（13），其使用清洁盒，然后在清洁工作之后将清洁盒带回原始盒式存储架（14,15）中的容纳部分。

公开(公告)号：US20020013887A1

公开(公告)日：2002-01-31

申请号：US09850897

申请日：2001-05-08

申请人： International Business Machines Corporation

发明人： Edison L. Ting

IPC分类号： G06F013/28 ,  G06F013/00 ,  G06F012/16 ,  G06F012/00 ,  G06F012/14 ,  G06F012/10 ,  G06F012/08 ,  G06F012/04 ,  G06F012/02 ,  G06F009/34 ,  G06F009/26

CPC分类号： G06F12/121

摘要： A data buffer memory management method and system is provided for increasing the effectiveness and efficiency of buffer replacement selection. Hierarchical Victim Selection (HVS) identifies hot buffer pages, warm buffer pages and cold buffer pages through weights, reference counts, reassignment of levels and ageing of levels, and then explicitly avoids victimizing hot pages while favoring cold pages in the hierarchy. Unlike LRU, pages in the system are identified by both a static manner (through weights) and in a dynamic manner (through reference counts, reassignment of levels and ageing of levels). HVS provides higher concurrency by allowing pages to be victimized from different levels simultaneously. Unlike other approaches, Hierarchical Victim Selection provides the infrastructure for page cleaners to ensure that the next candidate victims will be clean pages by segregating dirty pages in hierarchical levels having multiple separate lists so that the dirty pages may be cleaned asynchronously.

摘要翻译： 提供了一种数据缓冲存储器管理方法和系统，用于提高缓冲器更换选择的有效性和效率。 分层受害者选择（HVS）通过权重，参考计数，级别重新分配和级别老化来识别热缓冲页，热缓冲页和冷缓冲页，然后明确地避免了受害热页，同时有利于层次结构中的冷页。 与LRU不同，系统中的页面通过静态方式（通过权重）和动态方式（通过引用计数，级别重新分配和级别老化）来标识。 HVS通过允许页面同时受害于不同级别来提供更高的并发性。 与其他方法不同，分层受害者选择为页面清理器提供了基础设施，以确保下一个候选受害者将通过分离具有多个单独列表的分层级别的脏页面进行干净的页面，以便脏页面可以异步清除。

公开(公告)号：US20040148487A1

公开(公告)日：2004-07-29

申请号：US10707941

申请日：2004-01-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Masaya Mori ,  Shinpei Watanabe ,  Yoshihisa Takatsu ,  Toshio Sunaga

IPC分类号： G06F007/00 ,  G06F017/00 ,  G06F009/26 ,  G06F009/34 ,  G06F012/00

CPC分类号： G06F17/30949 ,  H04L29/12839 ,  H04L61/6022

摘要： Upon implementing a data registration into or a data retrieval from a data table (3) where first item data are registered along with corresponding second item data, there are used a first pointer table (1) where pointers to part of the registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a first hash function (6) to the first item data of the part of the registered data, and a second pointer table (2) where pointers to the other registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a second hash function (22) to the first item data of the other registered data.

公开(公告)号：US20040143722A1

公开(公告)日：2004-07-22

申请号：US10730619

申请日：2003-12-08

发明人： Burkhard Becker

IPC分类号： G06F009/34

CPC分类号： H03M13/6331 ,  H03M13/4169 ,  H03M13/6502 ,  H03M13/6569 ,  H04L25/03197

摘要： A method for transmitting data of a plurality of data types between a digital processor and a hardware arithmetic-logic unit with at least one associated table memory, first involves preselecting a base address in the table memory that (base address) is dependent on the data type of the data to be transmitted. This is followed by a read and/or write access to the table memory by taking the preselected base address as a starting point for computing the address used for the read/write access in the table memory for each access operation according to an arithmetic computation rule.

摘要翻译： 一种用于在数字处理器和硬件算术逻辑单元与至少一个相关联的表存储器之间传送多个数据类型的数据的方法，首先包括预先选择表存储器中的（基地址）取决于数据的基地址 要发送的数据类型。 之后，通过将预选的基地址作为计算用于每个访问操作的表存储器中的读/写访问的地址的起始点，根据算术计算规则对表存储器进行读和/或写访问 。

公开(公告)号：US20030196066A1

公开(公告)日：2003-10-16

申请号：US10446914

申请日：2003-05-27

申请人： Intel Corporation

发明人： Gregory S. Mathews

IPC分类号： G06F009/34

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to generate a hashed index, the index identifying an entry into two arrays. The first of the two arrays identifies a corresponding physical page address and the other array identifies a corresponding variable page address that in comparison to a variable portion of the virtual address, will indicate whether the entry in the first array has a matching entry. If the first array identifies a matching physical page address, then the physical page address is combined with the offset of the virtual address to yield a physical address translation of the virtual address.

公开(公告)号：US20030100316A1

公开(公告)日：2003-05-29

申请号：US10300754

申请日：2002-11-21

申请人： NEC CORPORATION

发明人： Satoshi Odamura

IPC分类号： H04Q007/20 ,  G06F015/16 ,  G06F012/10 ,  G06F009/34 ,  G01S001/00

CPC分类号： H04L67/36 ,  H04L67/04 ,  H04L67/18 ,  H04L69/329 ,  H04W4/029 ,  H04W92/08

摘要： A portable radio terminal includes a GPS signal processor for determining the position of the portable radio terminal, and requests a system server to transmit map image data and landmark data in the vicinity of the portable radio terminal. The system server transmits the map image data and landmark data separately to allow the display unit of the portable radio terminal to represent desired landmarks overlapped with the map image on the display unit.

摘要翻译： 便携式无线电终端包括用于确定便携式无线电终端的位置的GPS信号处理器，并且请求系统服务器在便携式无线电终端附近传送地图图像数据和地标数据。 系统服务器分别发送地图图像数据和地标数据，以允许便携式无线电终端的显示单元在显示单元上表示与地图图像叠加的所需地标。

公开(公告)号：US20020138799A1

公开(公告)日：2002-09-26

申请号：US10154210

申请日：2002-05-23

发明人： Katsuhiko Takano

IPC分类号： G11C029/00 ,  G06F009/26 ,  G06F009/34 ,  G06F012/00 ,  G06F012/02 ,  G06F012/04 ,  G06F012/08 ,  G06F012/10

CPC分类号： G11C29/56

摘要： A memory device testing apparatus transfers at high speed a fail signal from a failure analysis memory unit 100 to a memory failure remedy analysis unit 200. The failure analysis memory unit 100 has a data storage memory 110 and a compact memory 120. The data storage memory 110 is divided into at least two sub address spaces. The divided sub address spaces are assigned to the addresses in the compact memory 120. A address generation control unit reads data stored in the compact memory 120. An address generation unit 132 generates a memory address signal 143 based on a sub address signal 141 and a detail address signal 142. The detail address signal 142 is incremented by the address generation control unit 125. The data in the sub address space storing the fail signal is transferred to the memory failure remedy analysis unit 200. If the data read from the compact memory 120 does not contain failure information, the data stored in the corresponding sub address space is not transferred.

摘要翻译： 存储器件测试装置将故障分析存储器单元100的故障信号高速地传送到存储器故障补救分析单元200.故障分析存储单元100具有数据存储存储器110和紧凑型存储器120.数据存储存储器 110被划分为至少两个子地址空间。 划分的子地址空间被分配给紧凑型存储器120中的地址。地址生成控制单元读取存储在紧凑型存储器120中的数据。地址生成单元132基于子地址信号141生成存储器地址信号143， 详细地址信号142由地址产生控制单元125递增。存储故障信号的子地址空间中的数据被传送到存储器故障补救分析单元200.如果从紧凑型存储器读取的数据 120不包含故障信息，存储在相应子地址空间中的数据不传输。