公开(公告)号：US20050268185A1

公开(公告)日：2005-12-01

申请号：US10901609

申请日：2004-07-28

Applicant: David Vinke ,  Ekambaram Balaji

Inventor： David Vinke ,  Ekambaram Balaji

IPC: G11C29/00 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G11C11/41 ,  G11C29/32 ,  G11C2029/3202

Abstract: A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.

Abstract translation: 用于测试基于锁存器的随机存取存储器的方法和装置包括以下步骤：产生用于测试基于锁存器的随机存取存储器的扫描使能信号，并产生用于测试基于锁存器的随机存取存储器的扫描时钟信号，其中扫描时钟信号具有第一扫描时 移位周期的周期和捕获周期的第二扫描时钟周期。

公开(公告)号：US20050253639A1

公开(公告)日：2005-11-17

申请号：US10844298

申请日：2004-05-12

Applicant: Yuen Chan ,  Antonio Pelella ,  Jatinder Wadhwa ,  Otto Wagner

Inventor： Yuen Chan ,  Antonio Pelella ,  Jatinder Wadhwa ,  Otto Wagner

IPC: G11C7/10 ,  G11C11/34 ,  G11C11/419 ,  G11C29/32

CPC classification number: G11C7/1069 ,  G11C7/1051 ,  G11C11/41 ,  G11C11/419 ,  G11C29/32 ,  G11C2029/3202

Abstract: A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.

Abstract translation: 用于SRAM的脉冲到静态转换器，其中转换器锁存器由两个交叉耦合的互补FET对组成。 每对的FET在正电压源和地之间将漏极耦合到漏极。 SRAM读出放大器的输出状态作为一个FET对的栅极的输入耦合，由该输入建立的状态通过与另一个FET对的交叉耦合而锁存。

公开(公告)号：US20050222809A1

公开(公告)日：2005-10-06

申请号：US10812309

申请日：2004-03-30

Applicant: Teresa McLaurin ,  Frank Frederick

Inventor： Teresa McLaurin ,  Frank Frederick

IPC: G06F11/267 ,  G06F11/30

CPC classification number: G06F11/267 ,  G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C2029/3202

Abstract: In order to test the memory access signal connections between a data processing circuit, such as a processor core 2, and a memory 4, a subset of memory access signal connections 8 are provided with associated scan chain cells 10 so that they may be directly tested. The remainder memory access signal connections 12 which are common to all the expected configurations of the memory 4 are tested by being driven by the processor core 2 itself with data being passed through the memory and captured back within the processor core 2 for checking.

Abstract translation: 为了测试数据处理电路（例如处理器核心2）和存储器4之间的存储器访问信号连接，存储器访问信号连接8的子集被提供有相关联的扫描链单元10，使得它们可以被直接测试 。 存储器4的所有预期配置共同的剩余存储器访问信号连接12被处理器核心2本身驱动，数据被传送通过存储器并被捕获回到处理器核心2中进行检查。

公开(公告)号：US06928598B1

公开(公告)日：2005-08-09

申请号：US09880675

申请日：2001-06-13

Applicant: Ghasi R. Agrawal ,  Mukesh K. Puri

Inventor： Ghasi R. Agrawal ,  Mukesh K. Puri

IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G01R31/318555 ,  G11C29/72 ,  G11C2029/3202

Abstract: A system and method for protecting the values stored in a BISR repair block and, optionally, debugging the BISR repair logic without altering normal test flow is implemented by a circuit including a plurality of soft latches within the BISR repair block, the soft latches being coupled together to form a BISR scan chain for holding BISR repair information. A chip level scan enable signal and a scan hold control signal cooperate to control connection of the BISR scan chain to other scan chains during a scan test, so that the BSR repair information is held within the soft latches. A diagnose enable signal cooperating with the chip level scan enable signal and the scan hold control signal for enabling debugging of logic connecting the BISR scan chains.

Abstract translation: 用于保护存储在BISR修复块中的值以及可选地调试BISR修复逻辑而不改变正常测试流的系统和方法由包括BISR修复块内的多个软锁存器的电路实现，所述软锁存器被耦合 一起形成一个BISR扫描链，用于保存BISR修复信息。 在扫描测试期间，芯片级扫描使能信号和扫描保持控制信号协调控制BISR扫描链与其他扫描链的连接，使得BSR修复信息保持在软锁存器内。 诊断使能信号与芯片级扫描使能信号和扫描保持控制信号协同工作，以实现连接BISR扫描链的逻辑调试。

公开(公告)号：US06876221B2

公开(公告)日：2005-04-05

申请号：US10901035

申请日：2004-07-29

Applicant: Takeshi Ishigaki

Inventor： Takeshi Ishigaki

IPC: G01R31/02 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/24 ,  G11C29/02 ,  H01L21/822 ,  H01L27/04 ,  G01R31/26

CPC classification number: G06F11/24 ,  G01R31/2853 ,  G01R31/318505 ,  G01R31/318513 ,  G01R31/31855 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/3202 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor system includes a plurality of semiconductor chips, a first group of wirings, a second group of wirings and a connection rearrange wiring section. The first group of wirings interconnect the plurality of semiconductor chips. The second group of wirings are used for redundancy and interconnect the plurality of semiconductor chips. The connection rearrange wiring section includes a connection test circuit and connection rearrange circuit. The connection test circuit makes a test for connection between the plurality of semiconductor chips by means of the first group of wirings. The connection rearrange circuit makes unusable a wiring of the first group in which poor connection occurs and rearranges the connection between the semiconductor chips by use of the wiring of the second group when the poor connection is detected in the wiring of the first group by the connection test circuit.

公开(公告)号：US20050066243A1

公开(公告)日：2005-03-24

申请号：US10667879

申请日：2003-09-22

Applicant: Gordhan Barevadia ,  Anupama Agashe ,  Nikila Krishnamoorthy ,  Rubin Parekhji ,  Neil Simpson

Inventor： Gordhan Barevadia ,  Anupama Agashe ,  Nikila Krishnamoorthy ,  Rubin Parekhji ,  Neil Simpson

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G11C29/44

CPC classification number: G11C29/44 ,  G01R31/2856 ,  G01R31/318577 ,  G01R31/31905 ,  G11C2029/3202 ,  G11C2029/3602

Abstract: A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.

Abstract translation: 系统和方法提高了老化测试期间IC故障的可观察性。 扫描自动测试模式生成和内存自检模式在老化测试期间被监控，以提供观察选择性扫描链输出和存储器BIST状态输出的机制。

公开(公告)号：US20050041460A1

公开(公告)日：2005-02-24

申请号：US10645900

申请日：2003-08-20

Applicant: David Vinke ,  Ekambaram Balaji ,  Giuseppe Fornaciari

Inventor： David Vinke ,  Ekambaram Balaji ,  Giuseppe Fornaciari

IPC: G11C29/48 ,  G11C11/00

CPC classification number: G11C29/48 ,  G11C2029/3202

Abstract: A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.

Abstract translation: 基于锁存器的随机存取存储器包括输入数据寄存器; 耦合到输入数据寄存器的输入数据缓冲器; 耦合到所述输入数据缓冲器的锁存器阵列; 以及锁存阵列旁路多路复用器，用于响应于存储器扫描模式信号选择输入数据缓冲器和锁存器阵列之一，以在逻辑扫描测试期间从输入数据缓冲器生成基于锁存器的随机存取存储器的第一数据输出，以及 在存储器扫描测试期间，来自锁存器阵列的基于锁存器的随机存取存储器的第二数据输出。

公开(公告)号：US06834366B2

公开(公告)日：2004-12-21

申请号：US09957885

申请日：2001-09-21

Applicant: Nam-Seog Kim ,  Kwang-Jin Lee

Inventor： Nam-Seog Kim ,  Kwang-Jin Lee

IPC: G01R3128

CPC classification number: G11C29/12005 ,  G01R31/318572 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/3202

Abstract: A circuit and method for selectively outputting internal information in a semiconductor memory device comprising a test circuit such as a JTAG test circuit. The internal information is selectively output through a test pin of the test circuit during a normal operation mode of the semiconductor memory. The internal information of a semiconductor memory chip is output as either a digital or analog signal without having to add additional package pins.

Abstract translation: 一种用于选择性地输出半导体存储器件中的内部信息的电路和方法，包括诸如JTAG测试电路的测试电路。 在半导体存储器的正常操作模式期间，通过测试电路的测试引脚选择性地输出内部信息。 半导体存储器芯片的内部信息作为数字或模拟信号输出，而不必添加额外的封装引脚。

公开(公告)号：US06810498B2

公开(公告)日：2004-10-26

申请号：US10106052

申请日：2002-03-27

Applicant: Ryuji Shimizu

Inventor： Ryuji Shimizu

IPC: G01R328

CPC classification number: G11C29/12 ,  G11C2029/3202

Abstract: The outputs of selectors 230 to 23N are respectively connected to the data inputs DI0 to DIN of a RAM 10A. One inputs of selectors 540 to 54N are respectively connected to the data outputs DO0 to DON of the RAM 10A, the other inputs are connected to corresponding outputs of the selectors 230 to 23N. The outputs of the selectors 540 to 54N are connected to data inputs D of respective scan flip-flops 520 to 52N. Not in a RAM test mode, data input lines 210 to 21N are selected by the selectors 230 to 23N to provide to the data inputs DI0 to DIN of the RAM 10A and to the scan flip-flops 520 to 52N through the selectors 540 to 54N, respectively.

Abstract translation: 选择器230至23N的输出分别连接到RAM 10A的数据输入DI0至DIN。 选择器540至54N的一个输入分别连接到RAM 10A的数据输出DO0至DON，其他输入连接到选择器230至23N的相应输出。 选择器540至54N的输出连接到各扫描触发器520至52N的数据输入端D. 不是在RAM测试模式中，数据输入线210至21N由选择器230至23N选择，以通过选择器540至54N提供给RAM 10A的数据输入DI0至DIN，以及扫描触发器520至52N ， 分别。

公开(公告)号：US20040193979A1

公开(公告)日：2004-09-30

申请号：US10796480

申请日：2004-03-08

Applicant: Koninklijke Philips Electronics N.V.

Inventor： Daniel Lee Avery ,  Joel Patrick Bailey ,  Randall Pendley ,  Allyn Farmer

IPC: G01R031/28

CPC classification number: G01R31/31926 ,  G11C2029/3202

Abstract: A circuit testing approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths. According to an example embodiment of the present invention, a configurator arrangement (100) controls a configured circuit (110) by monitoring test signals and, in response, setting switches (115) on the configured circuit. In one implementation, the configurator circuit arrangement is programmed to automatically detect test signals (i.e., digital and/or JTAG test signals) and to control switches (115) for routing test data along a test circuit path on the configured circuit and/or between the configured circuit and an external circuit. With this approach, manual switching for routing the test signals is not necessary, which has been found to be useful in applications where access to the circuit paths for switching is difficult or impossible. In another implementation, a communications link (130) passes signals between the configurator circuit arrangement (100) and a user interface (140), including control signals from the user interface and data from the configured circuit (110). The configurator circuit arrangement (100) is further controllable (i.e., manually) or programmable by signals received from the user interface (140).

Abstract translation: 电路测试方法涉及可配置的开关控制，用于沿多个测试电路路径自动检测和布线测试信号。 根据本发明的示例性实施例，配置器装置（100）通过监视测试信号来控制配置的电路（110），并且作为响应，在配置的电路上设置开关（115）。 在一个实现中，配置器电路装置被编程为自动检测测试信号（即，数字和/或JTAG测试信号），并且控制开关（115）用于沿着配置的电路上的测试电路路径和/或介于 配置电路和外部电路。 使用这种方法，不需要用于路由测试信号的手动切换，这已经被发现在对于切换电路路径的访问困难或不可能的应用中是有用的。 在另一实现中，通信链路（130）在配置器电路装置（100）和用户接口（140）之间传递信号，包括来自用户接口的控制信号和来自配置的电路（110）的数据。 配置器电路装置（100）通过从用户接口（140）接收的信号可进一步控制（即，手动地）或可编程。